Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor. More specifically, the present invention provides an effective method for utilizing split channel MOS structures as an anti-fuse cell suitable for OTP memories.

Split-channel antifuse array architecture

A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.

High speed otp sensing scheme

An electronic device including: a semiconductor substrate having an array of gate conductors, each having a length and a width, comprised of dummy gate conductors and functional gate conductors extending in a widthwise direction, the gate conductors positioned substantially parallel to each other in the widthwise direction and periodically spaced apart a fixed distance in a direction substantially perpendicular to the widthwise direction.

Gate length proximity corrected device

Self-assembling materials, such as block copolymers, are used as mandrels for pitch multiplication. The copolymers are deposited over a substrate and directed to self-assemble into a desired pattern. One of the blocks forming the block copolymers is selectively removed. The remaining blocks are used as mandrels for pitch multiplication. Spacer material is blanket deposited over the blocks. The spacer material is subjected to a spacer etch to form spacers on sidewalls of the mandrels. The mandrels are selectively removed to leave free-standing spacers. The spacers may be used as pitch-multiplied mask features to define a pattern in an underlying substrate.

Pitch multiplication using self-assembling materials

A memory configuration includes a central connection area The central connection area is surrounded annularly by cell arrays having memory cells The memory configuration has compact external dimensions and is suitable, in particular, for a side ratio of 2:1 All the peripheral circuits are preferably disposed in the central connection area As a result, the propagation time differences between the peripheral circuits and the various cell arrays are relatively small

Memory configuration with a central connection area

The memory cells of an integrated memory are successively tested and immediately following the detection of a defect of the memory cell currently being tested, the affected row line or column line is replaced by programming one of the redundant lines. After a certain number of the redundant lines have been programmed, the programming of at least one of the redundant lines is canceled if a further defect is found. This redundant line is programmed for repairing a defect of another memory cell.

Method of repairing defective memory cells of an integrated memory

A refresh drive circuit for feeding refresh signals to a memory device has a refresh signal generator for generating a continuous sequence of refresh signals with a frequency which decreases as the temperature falls. The refresh drive circuit is connected to the memory device and as the temperature of the memory device falls, the frequency of refresh cycles decreases resulting in a decrease in current consumption.

Refresh drive circuit for a DRAM

A voltage level converter device for the conversion of an input signal, which is at a first voltage level, into an output signal, which is at a second voltage level that differs from the first voltage level, where the voltage level converter device has at least one transistor, and in which an additional transistor, controlled by a control signal at a voltage level corresponding to that of the input signal, is provided in a current path that is to be accordingly switched on or off when the output signal switches over for switching that path on or off.

Voltage level converter device

An integrated circuit comprises a bit line pair having two bit lines, a sense amplifier having at least one transistor, the sense amplifier amplifying a charge difference between the bit lines of the bit line pair; and a control unit connected to a substrate terminal of the at least one transistor, the control unit applying a substrate potential dependent on an operating state of the integrated circuit to the substrate of the at least one transistor.

Integrated circuit and method of operating such a circuit

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