We present a new signature scheme which is existentially unforgeable under chosen message attacks, assuming some variant of the RSA conjecture. This scheme is not based on "signature trees", and instead it uses the so called "hash-and-sign" paradigm. It is unique in that the assumptions made on the cryptographic hash function in use are well defined and reasonable (although non-standard). In particular, we do not model this function as a random oracle.

We construct our proof of security in steps. First we describe and prove a construction which operates in the random oracle model. Then we show that the random oracle in this construction can be replaced by a hash function which satisfies some strong (but well defined!) computational assumptions. Finally, we demonstrate that these assumptions are reasonable, by proving that a function satisfying them exists under standard intractability assumptions.

Secure Hash-and-Sign Signatures without the Random Oracle.

We present an efficient hardware prime generator that generates a prime p by combining trial division and Fermat test in parallel. Since the execution time of this parallel combination is greatly influenced by the number k of the smallest odd primes used in the trial division, it is important to determine the optimal k to create the fastest parallel combination. We present probabilistic analysis to determine the optimal k and to estimate the expected running time for the parallel combination. Our analysis is conducted in two stages. First, we roughly narrow the range of optimal k by using the expected values for the random variables used in the analysis. Second, we precisely determine the optimal k by using the exact probability distribution of the random variables. Our experiments show that the optimal k and the expected running time determined by our analysis are precise and accurate. Furthermore, we generalize our analysis and propose a guideline for a designer of a hardware prime generator to determine the optimal k by simply calculating the ratio of M to D, where M and D are the measured running times of a modular multiplication and an integer division, respectively.

Design and Analysis of Efficient Parallel Hardware Prime Generators

Context. Ensuring high-speed calculation by computer systems of the classical task of factorization of integer value on simple factorsrequires the development of effective algorithmic methods using the latest information technologies. Fast computation of factorization ofnumbers to provide high cryptocapability of information data, using multidimensional representation of one-dimensional sequences ofinformation data and other applications is sufficiently in demand in many practical tasks.Objective.The purpose of the work is to improve the method of trial divisions to compute the factorization of integer value with usingparallelization of computations and efficient use of computing resources of computer systems, which ensures faster computation of thevalues of prime factors of the decomposition.Method. It is proposed to use the residuals of each digit of the binary representation of the factorization number in order to check fordivisibility in the method performing of trial divisions into prime numbers.Results. The result of the study is to develop of a program of parallel execution of the factorization of integer value in computer systemswith multi-core processors.Conclusions. In the research, a method of checking for divisibility using the residuals of each digit of the binary representation of thefactorization number was applied, which allows for multi-threaded mode to execute the decomposition of the number into the factors. Thebasic idea of applying the corresponding mathematical apparatus is to use the residuals of the integer exponent of the number two from primenumbers. As a result, the accumulation of residuals is performed, which is checked for equality with the corresponding prime number and itsdegrees. The possibility of a multithreaded software organization for computing the number factorization ensures its parallel execution inmulti-core processors of computer systems

/pdf/obchislennia-faktorizatsiyi-chisla-v-multipotokovomu-rezhimi-2vlis4n1ky.pdf

Обчислення факторизації числа в мультипотоковому режимі на кристалі

This thesis answered how a fault attack targeting software used to program EEPROM can threaten hardware devices, for instance IoT devices. The successful fault attacks proposed in this thesis will certainly warn designers of hardware devices of the security risks their devices may face on the programming level

/pdf/fault-attacks-on-rsa-and-elliptic-curve-cryptosystems-ttw7q6b313.pdf

Fault attacks on RSA and elliptic curve cryptosystems

Context. Providing high-speed computation by computer systems of factorization of number into prime factors requires the development of effective algorithmic methods using computational technologies. Fast computation of factorization of numbers is used in such applications as, protection of information data, in algorithms of discrete transforms for transition from one to multidimensional computations and others. Objective. The purpose of the work is to analyze the implementation of technologies of multithreaded computation of factorization of integer value by the binary algorithm of the method of trial divisions using computer systems with multi-core processors and graphics accelerators. Method. A binary algorithm of trial divisions that uses the remainders of each digit of the binary representation of a number to perform a divisibility check on prime factors of the canonical factorization of number in parallel. Results. The analysis and comparison of multithreaded computations of software implementations of factorization of number by binary algorithm using hyper-threading, AMP C++, CUDA technologies in computer systems with multi-core processors and graphics accelerators. The results of the process of number factorization for multithreaded computing technologies using the same parallel core function are analyzed. Conclusions. In the study of realizations of number factorization by the binary algorithm in the multithreaded mode, the technology of hyper-threading calculations using multicore processors is most effectively performed. Heterogeneous computing using AMP C++ or CUDA technologies on computer systems and graphics accelerators requires consideration of GPU microarchitecture features for parallel computing core functions.

Analysis of the use of multithreaded computing technologies to factorize of numbers by a binary algorithm

SUMMARY As afe primep is a prime such that (p − 1)/2 is also a prime. A primality test or a safe primality test is normally a combination of trial division and a probabilistic primality test. Since the number of small odd primes used in the trial division affects the performance of the combination, researchers have studied how to obtain the optimal number of small odd primes to be used in the trial division and the expected running time of the combination for primality tests. However, in the case of safe primality tests, the analysis of the combination is more difficult, and thus no such results have been given. In this paper, we present the first probabilistic analysis on the expected running time and the optimal number of small odd primes to be used in the trial division for optimizing the tests. Experimental results show that our probabilistic analysis estimates the behavior of the

Probabilistic Analysis on the Optimal Combination of Trial Division and Probabilistic Primality Tests for Safe Prime Generation

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Design and Analysis of Efficient Parallel Hardware Prime Generators

Probabilistic Analysis on the Optimal Combination of Trial Division and Probabilistic Primality Tests for Safe Prime Generation