He Li

TL;DR: This paper analyses the problem of I/O operations within transactions, and proposes a hardware transactional memory system architecture based on multi-core processor and current cache coherent mechanisms that outperformed traditional lock-based programs.

TL;DR: In this article, the authors propose a method for blocking and awakening transaction threads in a hardware transactional memory system, which comprises the following steps of: arranging a transaction thread register in transaction supporting hardware and recording an identifier of a currently-executed transaction thread in the transactional thread register; when a blocked transaction thread is rescheduled and re-execussed and if the blocked thread is the same as the thread identifier in the register, continuing to submit the transaction; and if a blocked thread identifier is different from the registered transaction thread identifier, clearing a current transaction field and re

TL;DR: Efficient transaction nesting is one of the ongoing challenges for hardware transactional memory and a conditional partial rollback (CPR) scheme which supports conditional partialRollback without increasing hardware complexities significantly is proposed.

TL;DR: In this article, the authors propose a time sequence controlling method for parallel simulation of a cluster system, which comprises the following steps of: establishing a logical clock for all processes of a target system according to a simulation event captured by a host system; and then maintaining and updating the state of the logical clock according to the running state of a simulation time in the target system to acquire the running time of the processes.