An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.

Semiconductor device having doped epitaxial region and its methods of fabrication

Disclosed is an example method of manufacturing a semiconductor device. The disclosed example method includes depositing a gate insulating layer on an active region of a self aligned silicide (salicide) region and a non-self aligned silicide (salicide) region of a semiconductor substrate, forming a gate electrode, a poly crystal silicon layer, on the gate insulating layer of the self aligned silicide (salicide) region, and forming a spacer on both sidewalls of the gate electrode. The example method may further include depositing a silicide shielding layer on the gate insulating layer to cover the gate electrode and the spacer, forming a photoresist on the silicide shielding layer of the non-self aligned silicide (salicide) region, removing the silicide shielding layer of the self aligned silicide (salicide) region to expose the gate electrode, and performing an ion-implantation to render the poly crystal silicon layer of the gate electrode amorphous, without removing the photoresist on the silicide shielding layer of the non-self aligned silicide (salicide) region. The example method may further include removing the photoresist on the silicide shielding layer of the non-self aligned silicide (salicide) region and cleaning the semiconductor substrate and depositing a metal layer for forming a silicide layer and forming the silicide layer on the gate electrode of the self aligned silicide (salicide) region by annealing the semiconductor device.

Methods of manufacturing semiconductor devices

An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.

Method to control source/drain stressor profiles for stress engineering

A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.

Source/drain carbon implant and RTA anneal, pre-SiGe deposition

A diffusion layer for semiconductor devices is provided. In accordance with embodiments of the present invention, a semiconductor device, such as a transistor, comprises doped regions surrounded by a diffusion barrier. The diffusion barrier may be formed by recessing regions of the substrate and implanting fluorine or carbon ions. A silicon layer may be epitaxially grown over the diffusion barrier in the recessed regions. Thereafter, the recessed regions may be filled and doped with a semiconductor or semiconductor alloy material. In an embodiment, a semiconductor alloy material, such as silicon carbon, is selected to induce a tensile stress in the channel region for an NMOS device, and a semiconductor alloy material, such as silicon germanium, is selected to induce a compressive stress in the channel region for a PMOS device.

Diffusion layer for semiconductor devices

Diffusion layer for stressed semiconductor devices

Method for forming semiconductor devices

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Diffusion layer for semiconductor devices

Diffusion layer for stressed semiconductor devices

Method for forming semiconductor devices