Contact resistance is an important parameter to evaluate the feasibility of carbon nanotubes (CNT) field-effect transistors (FETs) in high performance logic applications. In this paper we make the systematic study of contact resistance of solution-processed CNT-FETs by transmission line method (TLM) and the Y-function method (YFM). TLM needs to calculate the voltage between source and drain electrodes of a group of devices with different channel length, but YLM only needs the transfer characteristic curve of a single device. The results by our calculation indicate that, the resistance obtained by YFM is larger than that obtained by TLM, which provides reference value for the selection of methods to find contact resistance in the future.

Comparative analysis of contact resistance of carbon nanotubes field-effect transistors

With the increasing number of lab burn-in samples, this paper proposes a parallel test approach for the problem that the single-device test board cannot meet the requirements of the JEDEC standard for the large number of samples with high efficiency. The designed FPGA control board independently separates 4 control SCAN signals, different SCAN chips perform read operations in sequence, and complete the operation in parallel. The experimental results show that, compared with the single-device test board, the MT test board can test 80 chips at the same time, which meets the requirements of the JEDEC standard, and reduces the requirement for hardware resources in the burn-in test, and improves test efficiency.

A Study on Parallel Test Approach for the Flash Burn-in Experiment in Laboratory

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Comparative analysis of contact resistance of carbon nanotubes field-effect transistors

A Study on Parallel Test Approach for the Flash Burn-in Experiment in Laboratory