Energy-proportional designs would enable large energy savings in servers, potentially doubling their efficiency in real-life use. Achieving energy proportionality will require significant improvements in the energy usage profile of every system component, particularly the memory and disk subsystems.

/pdf/the-case-for-energy-proportional-computing-4un8a5n8c1.pdf

The Case for Energy-Proportional Computing

Process variability has become a major challenge in nanometer technologies. Understanding process variability is therefore a key to designing successful low-power multi-million gate SoCs. An all-digital on-chip process control-monitor (PCM) that measures process variability is described.

An All-Digital On-Chip Process-Control Monitor for Process-Variability Measurements

The development of low-power (LP), low-voltage (LV) (or LPLV) digital MOS circuits, fueled by a strong need for highend microcomputers (MPUs) and explosive growth in portable systems, has surely contributed to the current boom in MOS large-scale integration (LSI). This article reviews such digital MOS circuits as they have been developed over the last 50 years, since the advent of integrated circuits (ICs). A particular emphasis is placed on MPUs, systems-on-a-chip (SoCs), and SRAMs and DRAMs; the discussion is based mainly on papers presented at the International Solid-State Circuits Conference (ISSCC) and the Symposium on VLSI Circuits. Flash memories that necessitate unique circuits for high density rather than low power and high speed are excluded.

A Historical Review of Low-Power, Low-Voltage Digital MOS Circuits Development

The dual-core PA6T-1682M system on chip (SoC) is the first design in the PWRficient family of high-performance, low-power processor designs that target server-class performance with low power consumption. the heart of the PA6T-1682M is the PA6T core, which implements the 64-bit IBM power architecture. The SoC implements extensive features that support embedded and mobile low-power applications.

Low-Power, High-Performance Architecture of the PWRficient Processor Family

Level shifter circuits are used to interface multiple voltage islands in many modern ICs or Systems-on-Chip (SoCs). Single-supply level shifters are being used to reduce the power routing resources and minimize the routing congestion at the chip level. A single-supply bidirectional level shifter aimed at low voltage which offers a wide voltage range (SS-WVRLS) is designed using standard commercial 90nm CMOS process. The proposed level shifter uses analog and digital circuit techniques to provide full voltage shifting range for any combination of supply voltages (VDDIN = VDD, VDDIN VDD) in any step size (paper shows 25mv step) with no requirement for special low-VT or high-VT devices, thus reducing the process cost. Post layout SPICE simulation comparison results show that proposed circuit is functional for full core supply voltage range (0.6V - 1.32V) compared to other published level shifters. The circuit was tested for robustness under process mismatch conditions by 1000 point global and local Monte Carlo simulations.

Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management

An SoC is presented with dual 2GHz Powertrade cores, coherent crossbar interconnect, 2MB L2 cache, and memory and I/O subsystem. The chip consumes a maximum of 25W of power. The 115mm2 die is implemented in a 65nm 8M process with low-power design techniques. Circuits to improve system performance under power constraints are discussed

A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems

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A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems