Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

Implanted B and P dopants in Si exhibit transient enhanced diffusion (TED) during annealing which arises from the excess interstitials generated by the implant. In order to study the mechanisms of TED, transmission electron microscopy measurements of implantation damage were combined with B diffusion experiments using doping marker structures grown by molecular-beam epitaxy (MBE). Damage from nonamorphizing Si implants at doses ranging from 5×1012 to 1×1014/cm2 evolves into a distribution of {311} interstitial agglomerates during the initial annealing stages at 670–815 °C. The excess interstitial concentration contained in these defects roughly equals the implanted ion dose, an observation that is corroborated by atomistic Monte Carlo simulations of implantation and annealing processes. The injection of interstitials from the damage region involves the dissolution of {311} defects during Ostwald ripening with an activation energy of 3.8±0.2 eV. The excess interstitials drive substitutional B into electric...

/pdf/physical-mechanisms-of-transient-enhanced-dopant-diffusion-zkysm82pgr.pdf

Physical mechanisms of transient enhanced dopant diffusion in ion-implanted silicon

This paper describes an automated process for designing analog electrical circuits based on the principles of natural selection, sexual recombination, and developmental biology. The design process starts with the random creation of a large population of program trees composed of circuit-constructing functions. Each program tree specifies the steps by which a fully developed circuit is to be progressively developed from a common embryonic circuit appropriate for the type of circuit that the user wishes to design. The fitness measure is a user-written computer program that may incorporate any calculable characteristic or combination of characteristics of the circuit. The population of program trees is genetically bred over a series of many generations using genetic programming. Genetic programming is driven by a fitness measure and employs genetic operations such as Darwinian reproduction, sexual recombination (crossover), and occasional mutation to create offspring. This automated evolutionary process produces both the topology of the circuit and the numerical values for each component. This paper describes how genetic programming can evolve the circuit for a difficult-to-design low-pass filter.

/pdf/automated-design-of-both-the-topology-and-sizing-of-analog-gfgycinj8i.pdf

Automated Design of Both the Topology and Sizing of Analog Electrical Circuits Using Genetic Programming

A simple CMOS circuit technique for realizing both linear transconductance and a precision square-law function is described. The circuit provides two separate outputs in the linear as well as square-law modes. The linear outputs both have a range of 100% or more of the total quiescent current value. The theory of operation is presented and effects of transistor nonidealities on the performance are investigated. Design optimization techniques are developed. Experimental results measured on nonoptimized prototypes are: distortion of 0.2% for input signals up to 2.4 V/SUB p-p/ in the case of linear transfer function and 1.3% in the case of the square-law transfer function, with a DC to -3-dB bandwidth of up to 20 MHz. Improved performance is expected when the optimization techniques developed are applied. The circuit is versatile in application: diverse applications are demonstrated in the fields of linear amplifiers, continuous-time filters, and nonlinear function implementation.

A versatile CMOS linear transconductor/square-law function

Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 /spl mu/m CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30%.

/pdf/reducing-mosfet-1-f-noise-and-power-consumption-by-switched-1dgtz1md7r.pdf

Reducing MOSFET 1/f noise and power consumption by switched biasing

A new measurement setup is presented that allows the observation of 1/f noise spectra in MOSFET's under switched bias conditions in a wide frequency band (10 Hz-100 kHz). When switching between inversion and accumulation, MOSFET's of different manufacturers invariably show reduced 1/f noise power density for frequencies below the switching frequency. At low frequencies (10 Hz), a 5-8 dB reduction in intrinsic 1/f noise power density is found for different devices, largely independent of the switching frequency (up to 1 MHz). The switched bias measurements render detailed wideband 1/f noise spectra of switched MOSFET's, which is useful for 1/f noise model validation and analog circuit design.

https://core.ac.uk/download/pdf/11453478.pdf

MOSFET 1/f noise measurement under switched bias conditions

This paper presents a transconductor suitable for implementation in submicron CMOS technology. The transconductor is nearly insensitive for the second-order effects of the MOS transistors, which become more and more prevalent in today's submicron processes. The transconductor relies on a differential pair with variable degeneration resistance, while the degeneration resistors are "soft-switched" by means of MOS transistors. The transconductance is continuously tunable. A transconductor, using a device in which the degeneration resistors and "soft switches" are merged, is optimized for a maximum tuning range and can be used in variable gain stages like in an automatic gain control (AGC) circuit. Besides, a third-order 5.5 MHz low-pass filter has been realized in a 0.5-/spl mu/m CMOS process using the "soft-switched" transconductor. At a 3.3 V supply voltage the filter dissipates 12 mW and the dynamic range equals 62 dB where the total harmonic distortion (THD) is -48 dB for an input voltage of 1 Vpp.

/pdf/a-cmos-soft-switched-transconductor-and-its-application-in-37x03l0hth.pdf

A CMOS "soft-switched" transconductor and its application in gain control and filters

This paper presents a mathematical analysis of the effect of limited precision analog hardware for weight adaptation to be used in on-chip learning feedforward neural networks. Easy-to-read equations and simple worst-case estimations for the maximum tolerable imprecision are presented. As an application of the analysis, a worst-case estimation on the minimum size of the weight storage capacitors is presented.

/pdf/precision-requirements-for-single-layer-feedforward-neural-448chkkbxj.pdf

Precision requirements for single-layer feedforward neural networks

The behavior of RTS noise in MOSFETs under large-signal excitation is experimentally studied. Our measurements show a significant transient effect, in line with earlier reports. We present a new physical model to describe this transient behavior and to predict RTS noise in MOSFETs under large-signal excitation. With only three model parameters the behavior is well described, contrary to existing models.

/pdf/modeling-of-rts-noise-in-mosfets-under-steady-state-and-fgyk3ot92u.pdf

Modeling of RTS noise in MOSFETs under steady-state and large-signal excitation

Silicon nitride layers with very low hydrogen content (less than 1 atomic percent) were deposited at near room temperature, from N2 and SiH4, with a multipolar electron cyclotron resonance plasma. The influences of pressure and nitrogen flow rate on physical and electrical properties were studied in order to minimize the hydrogen and oxygen content in the layers. The optimized layers were characterized by a refractive index of 1.98, a dielectric constant of 7.2, and Si/N ratio values of 0.78. The layers exhibited very good dielectric strength, which was confirmed by large breakdown fields of 12 MV/cm, very high resistivities of 1016 Omega cm, and maximum charges to breakdown values of 90 C/cm2. Increasing the deposition pressure and decreasing the N2 flow improved the SiN/Si interface, due to increased oxygen incorporation. The dominant conduction mechanism in the layers was the Poole-Frenkel effect. The critical field and the trap energy had similar dependencies on deposition pressure. Fowler-Nordheim tunneling occurred at high gate biases, for the layers deposited at the highest pressure of about 22 mTorr

Low hydrogen content silicon nitride films deposited at room temperature with an ECR plasma source

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