An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The authors survey the current state of phase change memory (PCM), a nonvolatile solid-state memory technology built around the large electrical contrast between the highly resistive amorphous and highly conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance, and yield characteristics. They introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. Challenges for the technology are addressed, including the design of PCM cells for low reset current, the need to control device-to-device variability, and undesirable changes in the phase change material that c...

Phase change memory technology

We survey the current state of phase change memory (PCM), a non-volatile solid-state memory technology built around the large electrical contrast between the highly-resistive amorphous and highly-conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance and yield characteristics. 
We introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. We then address challenges for the technology, including the design of PCM cells for low RESET current, the need to control device-to-device variability, and undesirable changes in the phase change material that can be induced by the fabrication procedure. We then turn to issues related to operation of PCM devices, including retention, device-to-device thermal crosstalk, endurance, and bias-polarity effects. Several factors that can be expected to enhance PCM in the future are addressed, including Multi-Level Cell technology for PCM (which offers higher density through the use of intermediate resistance states), the role of coding, and possible routes to an ultra-high density PCM technology.

A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

Non-volatile semiconductor storage device and method of manufacturing the same

A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

Nonvolatile memory device, operating method thereof and memory system including the same

An integrated circuit device, based on this architecture comprises a memory array with plural bit lines coupled with corresponding columns of memory cells in the array, plural reference lines, a plurality of access gate word lines coupled to access gates in corresponding rows in the array and a plurality of memory gate word lines coupled to memory gates in corresponding rows in the array. The memory cells in the array include respective access transistors having access gates and memory transistors having memory gates arranged in series between the corresponding bit lines and one of the plural reference lines. A memory transistor in a memory cell comprises a semiconductor body including a channel having a channel surface and a charge storing dielectric stack between the memory gate and the channel surface. The dielectric lamination layer comprises a tunneling dielectric layer connected with one of the memory gate and the channel surface and a blocking dielectric layer, and the dielectric lamination layer also comprises an electric charge trapping dielectric layer arrange on the tunneling dielectric layer.

Integrated circuit device

The physical model for field enhancement (FE) and the edge effects of body-tied FinFET charge-trapping NAND Flash devices are extensively studied in this paper. First, analytical equa- tions are derived to provide insight to the FE effect for FinFET devices, and these analytical results are validated by 3-D TCAD simulation and experimental verification. Next, complicated pro- gramming and erasing characteristics and transconductance and subthreshold slope (gm /SS) behaviors are completely explained by the nonuniform injection behavior along various corner edges in FinFET. FE allows high program and erase speed and larger memory window. On the other hand, the edge effect complicates the device DC I-V , as well as programming and erasing charac- teristics, and these must be taken into account in memory circuit design.

Physical Model of Field Enhancement and Edge Effects of FinFET Charge-Trapping

A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.

Non-volatile memory device with a threshold voltage change rate controlled by gate oxide phase

A semiconductor structure and a manufacturing method and an operating method of the same are provided. The semiconductor structure includes a substrate, a main body structure, a first dielectric layer, a first conductive strip, a second conductive strip, a second dielectric layer, and a conductive structure. The main body structure is formed on the substrate, and the first dielectric layer is formed on the substrate and surrounding two sidewalls and a top portion of the main body structure. The first conductive strip and the second conductive strip are formed on two sidewalls of the first dielectric layer, respectively. The second dielectric layer is formed on the first dielectric layer, the first conductive strip, and the second conductive strip. The conductive structure is formed on the second dielectric layer.

Semiconductor structure and manufacturing method and operating method of the same

A gate structure for a semiconductor device is provided. The gate structure includes a conductive structure. The conductive structure insulatively disposed over a substrate includes a middle portion and two spacer portions. The middle portion has a first surface and two second surfaces. The first surface is between the two second surfaces. The two spacer portions are respectively connected to the two second surfaces of the middle portion. A width of each of the two spacer portions gradually increases from top to bottom.

Gate structure of semiconductor device and methods of forming word line structure and memory

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