An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The authors survey the current state of phase change memory (PCM), a nonvolatile solid-state memory technology built around the large electrical contrast between the highly resistive amorphous and highly conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance, and yield characteristics. They introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. Challenges for the technology are addressed, including the design of PCM cells for low reset current, the need to control device-to-device variability, and undesirable changes in the phase change material that c...

Phase change memory technology

We survey the current state of phase change memory (PCM), a non-volatile solid-state memory technology built around the large electrical contrast between the highly-resistive amorphous and highly-conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance and yield characteristics. 
We introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. We then address challenges for the technology, including the design of PCM cells for low RESET current, the need to control device-to-device variability, and undesirable changes in the phase change material that can be induced by the fabrication procedure. We then turn to issues related to operation of PCM devices, including retention, device-to-device thermal crosstalk, endurance, and bias-polarity effects. Several factors that can be expected to enhance PCM in the future are addressed, including Multi-Level Cell technology for PCM (which offers higher density through the use of intermediate resistance states), the role of coding, and possible routes to an ultra-high density PCM technology.

A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

Non-volatile semiconductor storage device and method of manufacturing the same

A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

Nonvolatile memory device, operating method thereof and memory system including the same

Recently, we proposed a novel 3D AND-type Flash memory [1]–[3] architecture for 3D NOR Flash solution. In this work, we further propose a “write-in-place” (or “in-place write”) operation (like EEPROM) and demonstrate the feasibility. “Write-in-place” is to provide the same erase unit (page erase) as the program unit (page program). Thus to overwrite a page data the users just need one page erase followed by the page program, without the need to deal with a large erase unit (like NAND and NOR Flash memories). The in-place write does not require complex GC (garbage collection) algorithms by system controller, and can eliminate the write amplifications effect and improve the QoS (quality of service) of system performances. After optimization of BE-MANOS charge-trapping device, the in-place page write time can be minimized to around 110usec. Small neighbor-WL interferences, free from pattern loading effects and hot-carrier disturbs are merits of 3D AND architecture to enable write-in-place. We also suggest the future extensions of integrating ferroelectric memory FeFET device in the 3D AND architecture to further boost the in-place write speed to nearly 1 micro second at lower write voltages (∼5V).

Write-In-Place Operation and It's Advantages to Upgrade the 3D AND-type Flash Memory Performances

A 3D array of memory cells with one or more blocks is described. The blocks include a plurality of layers. The layers in the plurality include semiconductor strips which extend from a semiconductor pad. The layers are disposed so that the semiconductor strips in the plurality of layers form a plurality of stacks of semiconductor strips and a stack of semiconductor pads. Also, a plurality of select gate structures are disposed over stacks of semiconductor strips in the plurality of stacks between the semiconductor pad and memory cells on the semiconductor strips. In addition, different ones of the plurality of select gate structures couple the semiconductor strips in different ones of the stacks of semiconductor strips to the semiconductor pads in the plurality of layers. Further, an assist gate structure is disposed over the plurality of stacks between the select gate structures and the stack of semiconductor pads.

Assist gate structures for three-dimensional (3D) vertical gate array memory structure

Although conventional floating gate (FG) Flash memory has already gone into the sub-30 nm node, the technology challenges are formidable beyond 20nm. The fundamental challenges include FG interference, few-electron storage caused statistical fluctuation, poor short-channel effect, WL-WL breakdown, poor reliability, and edge effect sensitivity. Although charge-trapping (CT) devices have been proposed very early and studied for many years, these devices have not prevailed over FG Flash in the > 30nm node. However, beyond 20nm the advantage of CT devices may become more significant. Especially, due to the simpler structure and no need for charge storage isolation, CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the Moore’s law to continue for at least another decade. In this paper, we review the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss 3D memory architectures including the bit-cost scalable approach. Technology challenges and the poly-silicon thin film transistor (TFT) issues will be addressed in detail.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S1946427400002475

Overview of Advanced 3D Charge-trapping Flash Memory Devices

A memory device includes a plurality of memory cells arranged in series in a semiconductor body. First and second dummy memory cells arranged in series between a first string select switch and a first edge memory cell at a first end of the plurality of memory cells. The first dummy memory cell is adjacent the first edge memory cell, and the second dummy memory cell is adjacent the first string select switch. A channel line includes channels for the plurality of memory cells and the first and second dummy memory cells. Control circuitry is adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by applying a switching voltage to the first dummy memory cell, the switching voltage having a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level.

Programming NAND flash with improved robustness against dummy WL disturbance

Sub-40nm body-tied FinFET BE-SONOS NAND Flash is studied extensively. BE-SONOS offers efficient hole tunneling erase and excellent data retention. When integrated into a FinFET structure, the inherent field enhancement (FE) effect around the fin tip provides very faster program/erase speed. However, the non-uniform injection around the fin also greatly complicates the operation of FinFET BE-SONOS. In this work, the switching mechanisms at the fin tip, sidewall and bottom corner are examined in detail, thus providing insights to optimize the FinFET geometry. For the first time, we demonstrate that the ISPP together with self-boosting program-inhibit methods provide excellent Vt distribution control for MLC application for a FinFET CT device.

A Study of Sub-40nm FinFET BE-SONOS NAND Flash

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

Hang-Ting Lue

Author Tools

Chat about Author