This paper reviews several techniques used to reduce the in-band phase noise contribution of /spl Delta//spl Sigma/ fractional-N frequency synthesizers. The paper develops several practical techniques for specifying the noise and linearity of components used in a /spl Delta//spl Sigma/ fractional-N synthesizer. As an example, it presents a synthesizer with an in-band phase noise floor of -97 dBc/Hz@10 KHz for an RF output frequency of 2.432 GHz and a reference frequency of 16 MHz. The synthesizer has a frequency resolution of 61 Hz and an on-chip crystal oscillator. The synthesizer was implemented in a 0.35-/spl mu/m SiGe process and consumes 6 mA from a 3 V supply. The in-band phase-noise, spurs, and power consumption of this synthesizer are each low and comparable to the state of the art.

/pdf/techniques-for-in-band-phase-noise-reduction-in-spl-delta-1q5shyh5j6.pdf

Techniques for in-band phase noise reduction in /spl Delta//spl Sigma/ synthesizers

A finite-modulo fractional-N PLL utilizing a low-bit high-order DeltaSigma modulator is presented. A 4-bit fourth-order DeltaSigma modulator not only performs non-dithered 16-modulo fractional-N operation but also offers less spur generation with negligible quantization noise. Further spur reduction is achieved by charge compensation in the voltage domain and phase interpolation in the time domain, which significantly relaxes the dynamic range requirement of the charge pump compensation current. A 1.8-2.6 GHz fractional-N PLL is implemented in 0.18 mum CMOS. By employing high-order deterministic DeltaSigma modulation and hybrid spur compensation, the spur level of less than -55 dBc is achieved when the ratio of the bandwidth to minimum frequency resolution is set to 1/4. The prototype PLL consumes 35.3 mW in which only 2.7 mW is consumed by the digital modulator and compensation circuits.

A hybrid spur compensation technique for finite-modulo fractional-N phase-locked loops

A MASH 111 delta-sigma modulator (DSM) is widely used in a fractional-N frequency synthesizer. This brief presents a low-complexity delta-path design in a MASH 111 modulator by simply recoding all carry output signals from accumulators. Compared with the prior approach, the hardware complexity of the proposed delta path is reduced to 53.4% of the prior approach. For frequency synthesizers with limited channels or for the pipelined DSM with accumulators possessing long word lengths, this saving is significant.

Hardware Simplification to the Delta Path in a MASH 111 Delta–Sigma Modulator

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.

Integrated radio frequency synthetizers for wireless applications

The objective of this work is to present practical design consideration of fractional-N frequency synthesis focusing on different aspects from integer-N frequency synthesizer design. In this work, a ΔΣ fractional-N frequency synthesis technique for high spectral purity is primarily considered. Th ΔΣ fractional-N synthesizer offers several advantages over integer-N synthesizers and conventional fractional-N synthesizers. However, superior performance of the ΔΣ fractional-N synthesizer can be possibly limited by noise coupling, nonlinearity, and out-of-band phase noise performance. Design efforts and system perspectives both for the ΔΣ modulator and the PLL are needed to overcome those issues. System and circuit design aspects in ΔΣ fractional-N synthesizer design have been addressed followed by experimental hardware results.

Practical Design Aspects in Fractional-N Frequency Synthesis

A 2 GHz fractional-N frequency synthesizer for telecommunications applications is presented. The synthesizer includes a multiple-modulus CMOS prescaler capable of operating at input frequencies of up to 2.15 GHz with a power dissipation of 12.5 mW, a third-order MASH ΔΣ-modulator that controls the modulus of the prescaler, and a phase detector and chargepump that doesn't suffer from dead-zone problems. The synthesizer achieves a close-in phase noise of-79 dBc/Hz while dissipating only 22.6 mW from a 2.7 V supply. The synthesizer has been implemented in a 0.35 µm CMOS technology.

A 2 GHz ΔΣ fractional-N frequency synthesizer in 0.35 µm CMOS

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A 2 GHz ΔΣ fractional-N frequency synthesizer in 0.35 µm CMOS