The present device provides for a dynamically configurable communication network having a multi-processor parallel processing system having a serial communication network and a high speed parallel communication network. The serial communication network is used to disseminate commands from a master processor (100) to a plurality of slave processors (200) to effect communication protocol, to control transmission of high density data among nodes and to monitor each slave processor's status. The high speed parallel processing network is used to effect the transmission of high density data among nodes in the parallel processing system. Each node comprises a transputer (104), a digital signal processor (114), a parallel transfer controller (106), and two three-port memory devices. A communication switch (108) within each node (100) connects it to a fast parallel hardware channel (70) through which all high density data arrives or leaves the node.

Parallel processing data network of master and slave transputers controlled by a serial control network

A portable computer system wherein the printer port can be used, at the user's option, not only for connection to a printer, but also for connection to an external floppy disk drive. If the BIOS determines that there is an external floppy drive attached, the BIOS disables the normal operation of the parallel port in order to allow the external floppy to operate.

Portable computer with automatic adaption to different device types on a standard port

An isochronous data pipe provides a bi-directional path for data between an application and a bus structure. The isochronous data pipe includes the ability to send, receive and perform manipulations on any isochronous stream of data, including data on any number of isochronous channels. The isochronous data pipe is a programmable sequencer that operates on the stream of isochronous data as it passes through the isochronous data pipe. The isochronous data pipe is programmed by an application to perform specific operations on the stream of data before the data is either transmitted across the bus structure or sent to the application, thereby pre-processing and manipulating the data before it is delivered to its destination. The operations are performed on both the packet header and the data field of the data packet. The isochronous data pipe can be stopped and started on the occurrence of specific events. In an alternate embodiment of the present invention, the isochronous data pipe is programmed to send and receive both isochronous and asynchronous data, including generating requests and appropriate packet headers.

Isochronous data pipe for managing and manipulating a high-speed stream of isochronous data flowing between an application and a bus structure

A battery detect circuit (32) is connected to the battery with the current input to the battery and extracted from the battery measured with a sense resistor (50) and then converted to charge and discharge pulses with a V/F converter (52) A microcontroller (64) is operable to increment a Nominal Available Charge (NAC) register (180) during a charge operation, and to increment a Discharge Count Register (DCR) (184) during a discharge operation The NAC register (180) indicates the available charge, which value is output to a display (34) The maximum value to which the NAC value can rise is limited by a value stored in the last measured discharge register (182) This value represents the value stored in the DCR (184) whenever the battery is discharged from an apparent full state to a fully discharged state This results in a qualified transfer to the LMD register (182) such that no knowledge of the actual battery charge is necessary The charge rate is varied as both a function of temperature, voltage and also of the state of charge A fast charge rate is initiated when the charge state is above a predetermined low voltage threshold and less than full When the charge state reaches a level within approximately 80% of full charge, the charge rate is reduced At full capacity, the charge rate is further reduced to a top off charge rate which continues for approximately two hours If the temperature falls below a predetermined low temperature threshold, the charge rate is again reduced to a safe, slow, effective rate Trickle charge is provided to replenish charge adaptively in accordance with a self-discharge counter The trickle charge operates to momentarily pulse the battery (10) at a predetermined charge rate

Method and apparatus for monitoring batttery capacity with charge control

An application programming interface implements and manages isochronous and asynchronous data transfer operations between an application and a bus structure. During an asynchronous transfer the API includes the ability to transfer any amount of data between one or more local data buffers within the application and a range of addresses over the bus structure using one or more asynchronous transactions. An automatic transaction generator may be used to automatically generate the transactions necessary to complete the data transfer. The API also includes the ability to transfer data between the application and another node on the bus structure isochronously over a dedicated channel. During an isochronous data transfer, a buffer management scheme is used to manage a linked list of data buffer descriptors. This linked descriptor list can form a circular list of buffers and include a forward pointer to the next buffer in the list and a backward pointer to the previous buffer in the list for each buffer. The linked descriptor list may also form a linear list to which the application can append additional buffers or remove existing buffers from the list. During isochronous transfers of data, the API provides implementation of a resynchronization event in the stream of data allowing for resynchronization by the application to a specific point within the data. Implementation is also provided for a callback routine for each buffer in the list which calls the application at a predetermined point during the transfer of data.

Application programming interface for data transfer and bus management over a bus structure

An arbitration circuit (10) is provided for selecting between a serial port (19) and a parallel port (21) for interface with a system port (17) having a system data bus (14) and a system address bus (16). A RAM (12) is supported by the buses (14) and (16). The arbiter (10) is operable to store a count value in an arbitration byte (38) which is addressable by the parallel port (21). The serial port (19) is operable to transfer data through a serial/parallel converter (30) to the system data bus (14) and system address bus (16) during a serial port access window. The parallel port (21) is allowed to access the system data bus and address bus at all other times. A count value indicating the duration of time before occurrence of the access window is stored in the arbitration byte (38) and is accessible by the parallel port and a parallel CPU (24) to determine when address and data information can be transmitted to the arbiter (10) for transfer to RAM (12). This provides an interleaved operation whereby the parallel port (21) can access the system during collection of data in the serial/parallel converter (30).

Interleaved arbitration scheme for interfacing parallel and serial ports to a parallel system port

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Interleaved arbitration scheme for interfacing parallel and serial ports to a parallel system port