Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here.

/pdf/the-2018-gan-power-electronics-roadmap-2iunv619fh.pdf

The 2018 GaN power electronics roadmap

Superjunction has arguably been the most creative and important concept in the power device field since the introduction of the insulated gate bipolar transistor (IGBT) in the 1980s. It is the only concept known today that has challenged and ultimately proved wrong the well-known theoretical study on the limit of silicon in high-voltage devices. This paper deals with the history, device and process development, and the future prospects of Superjunction technologies. It covers fundamental physics, technological challenges as well as aspects of design and modeling of unipolar devices, such as CoolMOS. The superjunction concept is compared to other methods of enhancing the conductivity of power devices (from bipolar to employment of wide-bandgap materials) to derive its set of benefits and limitations. This paper closes with the application of the superjunction concept to other structures or materials, such as terminations, superjunction IGBTs, or silicon carbide Field Effect Transistors (FETs).

Superjunction Power Devices, History, Development, and Future Prospects

Wireless communication has led to an explosive growth of emerging consumer and military applications of radio frequency (RF), microwave and millimeter wave circuits and systems. Future personal (hand-held) and ground communications systems as well as communications satellites necessitate the use of highly integrated RF front-ends, featuring small size, low weight, high performance and low cost. Continuing chip scaling has contributed to the extent that off-chip, bulky passive RF components, such as high-Q inductors, ceramic and SAW filters, varactor diodes and discrete PIN diode switches, have become limiting. Micro-machining or MEMS technology is now rapidly emerging as an enabling technology to yield a new generation of high-performance RF-MEMS passives to replace these off-chip passives in wireless communication (sub)systems. This paper reviews the progress in RF-MEMS from a device and integration perspective. The worldwide state-of-the-art of RF-MEMS devices including switches, variable capacitors, resonators and filters are described. Next, it is stipulated how integration of RF-MEMS passives with other passives (as inductors, LC filters, SAW devices, couplers and power dividers) and, active circuitry (ASICs, RFICs) can lead to the so-called RF-MEMS system-in-a-package (RF-MEMS-SiP) modules. The evolution of the RF-MEMS-SiP technology is illustrated using IMEC's microwave multi-layer thin-film MCM-D technology which today already serves as a technology platform for RF-SiP.

https://iopscience.iop.org/article/10.1088/0960-1317/13/4/323/pdf

MEMS for wireless communications: 'from RF-MEMS components to RF-MEMS-SiP'

The historical and technological development of the ubiquitous trench power MOSFET (or vertical trench VDMOS) is described. Overcoming the deficiencies of VMOS and planar VDMOS, trench VDMOS innovations include pioneering efforts in reactive ion etching and oxidation of the silicon trench gate, polysilicon fill and recessed etchback, unit cell and distributed voltage clamping to protect the trench gate, and scaling active cells to high densities using deep submicron fabrication. Thereafter, gate–drain engineered trench VDMOS improved high-frequency switching capability with lower gate charge utilizing nonuniform gate oxides, field shaping, and charge balancing (superjunction, RSO) methods. The recent adaptation of trench gates in wide bandgap unipolar devices is also described.

The Trench Power MOSFET: Part I—History, Technology, and Prospects

GaN-on-Si power switching transistors that use carbon-doped epitaxy are highly vulnerable to dynamic $\text{R}_{ON}$ dispersion, leading to reduced switching efficiency. In this paper, we identify the causes of this dispersion using substrate bias ramps to isolate the leakage paths and trapping locations in the epitaxy and simulation to identify their impact on the device characteristics. It is shown that leakage can occur both vertically and laterally, and we suggest that this is associated not only with bulk transport, but also with extended defects as well as hole gases at heterojunctions. For exactly the same epitaxial design, it is shown using a “leaky dielectric” model that depending on the leakage paths, dynamic $\text{R}_{ON}$ dispersion can vary between insignificant and infinite. An optimum leakage configuration is identified to minimize dispersion requiring a resistivity which increases with depth in the buffer stack. It is demonstrated that leakage through the undoped GaN channel is required over the entire gate to drain gap, and not just under the contacts, in order to fully suppress dispersion.

/pdf/leaky-dielectric-model-for-the-suppression-of-dynamic-r-2ho0i94ufm.pdf

“Leaky Dielectric” Model for the Suppression of Dynamic $R_{\mathrm{ON}}$ in Carbon-Doped AlGaN/GaN HEMTs

This paper reports on an industrial DHEMT process for 650V rated GaN-on-Si power devices. The MISHEMT transistors use an in-situ MOCVD grown SiN as surface passivation and gate dielectric. Excellent off-state leakage, on-state conduction and low device capacitance and dynamic Ron is obtained. Initial assessment of the intrinsic reliability data on the in-situ SiN is provided.

An industrial process for 650V rated GaN-on-Si power devices using in-situ SiN as a gate dielectric

Enhancement mode 650V rated p-GaN gate HEMTs are fabricated on 200 mm p+ Si substrates by using an industrial, Au-free process. The devices show true e-mode performance, with a high V t of 2.8 V, low off-state leakage current and are dynamic R DS-ON free over the complete V DS and temperature range. High temperature reverse bias (HTRB) testing is done on-wafer and after packaging. For the first time, 650 V e-mode power HEMTs realized on 200 mm Si substrates, show industry ready device performance and pass 1008 hour reliability testing, at V GS =0 V, V DS =650 V.

An industry-ready 200 mm p-GaN E-mode GaN-on-Si power technology

Reports on wafer-level packaged RF-MEMS switches fabricated in a commercial CMOS fab. Switch fabrication is based on a metal surface micromachining process. A novel wafer-level packaging scheme is developed, whereby the switches are housed in on-chip sealed cavities using benzocyclobutene (BCB) as the bonding and sealing material. Measurements show that the influence of the wafer-level package on the RF performance can be made very small.

Wafer-level packaged RF-MEMS switches fabricated in a CMOS fab

This paper for the first time reports on a novel “local” charge balanced trench-based super junction transistor. The local charge balance is achieved by selectively growing thin highly-doped n-type and p-type layers in a deep trench structure. The final charge-balanced trench structure is finished with an oxide-sealed airgap. Devices rated at 10A with V bd =730V and a Ron=23 mΩ.cm2 are demonstrated.

UltiMOS: A local charge-balanced trench-based 600V super-junction device

This paper describes a wafer-to-wafer 0-level packaging method to realize low-profile, near hermetically sealed packaged devices using BenzoCycloButene (BCB) as the bonding and sealing material. The technique is fully described, and the bond is mechanically tested in terms of shear strength and hermeticity. Silicon caps as thin as 100 /spl mu/m have been successfully bonded to silicon device wafers. Shear strength as high as 20 MPA have been measured, and all tested packaged devices were gross leak tight.

Wafer-scale 0-level packaging of (RF-)MEMS devices using BCB

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