A comprehensive 45 nm short-flow test chip was designed and is currently used to improve defect-limited yield. In a novel development to reduce test time, the DC test structures are tested in parallel mode on a functional test platform, resulting in a 5x reduction in test time over conventional parametric testing. The large critical area enables accurate measurement of defect densities down to the ppb-level, while the reduced cycle time of this short-flow test chip makes it an excellent routine defect monitor as well as a test vehicle for evaluating process changes.

Short-flow test chip utilizing fast testing for defect density monitoring in 45nm

We describe the development and use of various test structures for 32nm yield enhancement. These DC defect test structures are tested in parallel mode on a functional tester using special V/I and Pico-Amp measurement cards. This new test method provides measurement accuracy as high as ± 10 pA along with up to 9x reduction in test time over conventional parametric testing. The large critical area enables reliable estimation of defect densities by failure mechanism.

Test Structures Utilizing High-Precision Fast Testing For 32nm Yield Enhancement

Electrical characterization remains a key element in technology development and manufacturing of integrated circuits. Contact chain is a well known part of the diagnostic set of test structures used across many generations of silicon processes. Implementation of such test structures becomes challenging in new technologies with 3-D devices, like FinFET. Contacts to active regions of such devices are inherently dependent on the architecture of epitaxial raised source and drain and for proper characterization require the presence of transistor gates, which set the environment for contacts. This paper describes a new type of test structure, so-called gated contact chains, developed for contact process characterization in FinFET technologies. Instead of simple chain of contacts, each structure contains a series of active devices with common gate electrode used to turn on the chain of transistors to enable measurement of chain resistance. To discriminate between chain failures caused by an open contact or by other mechanisms (e.g., bad transistor with very high threshold voltage) a series of measurement under various test conditions was performed and analysed. In order to overcome a limitation of the contact chain size and enable data collection from larger sample of contacts, we proposed to implement the gated chains in addressable arrays, increasing their density and failure rate observability. Finally, the paper presents the examples of electrical failure modes detected by those chains in FinFET process.

Contact Chains for FinFET Technology Characterization

The continuing rise in the number and complexity of test structures required to characterize every new technology generation demands at least a commensurate increase in test throughput. At IBM, various 32nm yield test structures are being tested on a functional test platform using customized Source Measurement Units (SMU) that allow parallel current measurement on up to 100 pins. This novel method improves test throughput as much as 9X over traditional parametric testing while offering current measurement resolution down to 100 fA. The test structures described herein help accelerate yield learning by enabling characterization of yield-loss mechanisms and rapid evaluation of yield improvement actions.

32nm yield learning using efficient parallel-test structures

Contact Chain is a well known element of the diagnostic set of test structures used across many generations of silicon processes. Implementation of such test structures becomes challenging in new technologies with 3D devices, like FinFET. Contacts to active regions of such devices are inherently dependent on the architecture of epitaxial raised source and drain and for proper characterization require the presence of transistor gates, which set the environment for contacts. This paper describes examples of test structures for contact process development for FinFET technologies. Instead of simple chain of contacts, each structure contains a series of active devices with common gate electrode used to turn on the chain of transistors to enable measurement of chain resistance. To discriminate between chain failures caused by an open contact or by other mechanisms (e.g. bad transistor with very high threshold voltage) a series of measurement under various test conditions is performed and analysed to extract the contact failure rate. We also demonstrate the application of such structures in FinFET process characterization.

Gated contact chains for process characterization in FinFET technologies

Complexity of integrated circuits has led to hundreds of millions of transistors, wiring lines, and layer to layer via connections on every chip. To allow accurate yield evaluation, it is required that process characterization test chips grow in complexity as well which has let to a significant bottleneck in testing them. Wafers that could be tested in less than two hours in a 0.35/spl mu/m technology now require 10 hours and more in a 0.13/spl mu/m technology. This paper will present methods how test structures can be redesigned to better support testing. Based on those we will present modified test algorithms that will significantly reduce the test time by 50% and more, which will accelerate data analysis and increases efficient use of parametric test systems.

Test time reduction methods for yield test structures

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Test time reduction methods for yield test structures