Japanese journal of applied physics : JJAP online.

Provided is a semiconductor device including first to sixth capacitors, first to fourth wirings, first and second sense amplifiers, and a memory cell array over the first and second sense amplifiers. The first wiring is electrically connected to the memory cell array, one electrode of the first capacitor, the third wiring via a source and a drain of a first transistor, the fourth wiring via the fifth capacitor, and the second wiring via the first sense amplifier. The second wiring is electrically connected to one electrode of the second capacitor, the fourth wiring via a source and a drain of a second transistor, and the third wiring via the sixth capacitor. The third wiring is electrically connected to one electrode of the third capacitor, and the fourth wiring via the second sense amplifier. The fourth wiring is electrically connected to one electrode of the fourth capacitor.

Semiconductor device or electronic component including the same

Crystalline IGZO thin films were first used in consumer products successfully by a joint development with Sharp Corporation. The crystalline IGZO thin films have a CAAC (C-axis Aligned Crystal) structure, a novel crystalline structure without clear grain boundaries. We examined the mechanism of formation of the structure on a given surface and fabricated TFTs using CAAC-IGZO. We examined their characteristics and found that the TFTs had little variation in characteristic and high reliability even with a short channel length L. Application of CAAC-IGZO to various LSIs is expected.

/pdf/a-possibility-of-crystalline-indium-gallium-zinc-oxide-1h907zzgwe.pdf

A possibility of crystalline Indium-Gallium-Zinc-Oxide

A memory device in which the number of films is reduced. The memory device includes a circuit and a wiring. The circuit includes a first memory cell and a second memory cell. The first memory cell includes a first transistor, a second transistor, and a first capacitor. The second memory cell includes a third transistor, a fourth transistor, and a second capacitor. The second memory cell is stacked over the first memory cell. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the first capacitor. One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor and the second capacitor. A gate of the first transistor and a gate of the third transistor are electrically connected to the wiring.

Memory device or electronic device including the same

Memory device comprising stacked memory cells and electronic device including the same

A state retention flip flop which retains its state without power, has zero area overhead, a theoretical zero backup time and simple power control is demonstrated in a Normally-Off 32-bit CPU.

Zero Area Overhead State Retention Flip Flop Utilizing Crystalline In-Ga-Zn Oxide Thin Film Transistor with Simple Power Control Implemented in a 32-bit CPU

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Zero Area Overhead State Retention Flip Flop Utilizing Crystalline In-Ga-Zn Oxide Thin Film Transistor with Simple Power Control Implemented in a 32-bit CPU