In this overview, the low-frequency noise behaviour of devices fabricated in silicon-on-insulator technologies is described. The different potential noise sources are analysed and illustrated by experimental results, mainly obtained on MOSFETs. Some SOI-specific noise behaviour is highlighted, as for instance the kink-related excess low-frequency noise overshoot. It is shown furthermore that SOI MOSFETs suffer from so-called random telegraph signals, which can originate from the front- or the back-gate dielectric, or from defects located in the thin Si active layer. The impact of the substrate type (SIMOX, bonded, ZMR,…) is discussed. At the same time, it is shown that the used technology and device structure can have a pronounced effect on the LF noise performance. Finally, the response of SOI MOSFETs on ionizing radiation (γs, X-rays,…) is studied through the LF noise degradation, in view of radiation-hardened applications.

The low-frequency noise behaviour of silicon-on-insulator technologies

Progress in CMOS technology and in fine pitch bump bonding has made
possible the development of high granularity single photon counting detectors for
X-ray imaging. This thesis studies the design a ...

Design and Characterization of 64K Pixels Chips Working in Single Photon Processing Mode

The innovation in monolithic and hybrid semiconductor ‘micropattern’ or ‘reactive’ pixel detectors for tracking in particle physics was actually to fit logic and pulse processing electronics with μW power on a pixel area of less than 0.04 mm 2 , retaining the characteristics of a traditional nuclear amplifier chain. The ns timing precision in conjunction with local memory and logic operations allowed event selection at >10 MHz rates with unambiguous track reconstruction even at particle multiplicities >10 cm −2 . The noise in a channel was ∼100 e − rms and enabled binary operation with random noise ‘hits’ at a level 75 μm ×500 μm down to 34 μm ×125 μm have been used by different teams. In binary mode a tracking precision from 6 to 14 μm was obtained, and using analog interpolation one came close to 1 μm . Earlier work, still based on charge integrating imaging circuits, provided a starting point. Two systems each with more than 1 million sensor + readout channels have been built, for WA97-NA57 and for the Delphi very forward tracker. The use of 0.5 μm and 0.25 μm CMOS and enclosed geometry for the transistors in the pixel readout chips resulted in radiation hardness of ∼2 Mrad , respectively, >30 Mrad .

Semiconductor micropattern pixel detectors: a review of the beginnings

Ultra-thin ionizing radiation detector, and processes of manufacturing such detector. The detector includes a stack made up of a substrate, an insulting layer and a thin superficial layer of silicon, a detection diode being fabricated in the superficial layer.

Ultra-thin ionizing radiation detector and methods for making same

Silicon-on-insulator (SOI) technology is being investigated for monolithic pixel device fabrication. The SOI wafers by UNIBOND allow the silicon resistivity to be optimized separately for the electronics and detector parts. We have fabricated pixel detectors using fully depleted SOI (FD-SOI) technology provided by OKI Semiconductor Co. Ltd. The first pixel devices consisting of 32times32 matrix with 20 mum times 20 mum pixels were irradiated with 60Co gamma's up to 0.60 MGy and with 70-MeV protons up to 9.3times10 60Co p/cm2. The performance characterization was made on the electronics part and as a photon detector from the response to reset signals and to laser. The electronics operation was affected by radiation-induced charge accumulation in the oxide layers. Detailed evaluation of the characteristics changes in the transistors was separately carried out using transistor test structures to which a wider range of irradiation, from 0.12 kGy to 5.1 MGy, was made with 60Co gamma's.

Radiation Resistance of SOI Pixel Devices Fabricated With OKI 0.15 $\mu {\rm m}$ FD-SOI Technology

A new approach to monolithic pixel detectors, based on silicon on insulator (SOI) wafers with high resistivity substrate, is being pursued by the CERN RD19 collaboration. The fabrication methods and the results of the electrical evaluation of the SOI-MOSFET devices and of the detector structures fabricated in the bulk are reported. The leakage current of the high-resistivity PIN-diodes is kept of the order of 5 to 10 nA/cm/sup 2/. The SOI preparation processes employed-SIMOX (separation by implantation of oxygen) and ZMR (zone melting recrystallization)-produce working electronic circuits, and appear to be compatible with the fabrication of detectors of suitable quality. >

Integration of CMOS-electronics and particle detector diodes in high-resistivity silicon-on-insulator wafers

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Integration of CMOS-electronics and particle detector diodes in high-resistivity silicon-on-insulator wafers