A load sharing system which minimizes overall costs by assigning segments of a divisible load to distributed processor platforms based on the resource utilization cost of each processor platform. The distributed processor platforms are connected via data links which also have associated resource utilization costs. A controller divides a divisible load or task and assigns each segment of the load or task to a processor platform based on the processor platform's resource utilization cost and data link cost. After the initial allocation, an optimizing reallocation is performed to reduce the overall monetary cost processing the load or task. The optimization can be performed using a pair-wise swapping technique.

Load sharing controller for optimizing resource utilization cost

A load sharing system (100) which minimizes overal costs by assigning segments of a divisible load to distributed processors (105, 107, 109) based on the monetary cost of each processor. The distributed processors are connected to a network such as a local area network (114) or the Internet. A controller (103) divides a divisible load and assigns each segment of the load to a processor based on the processor's monetary cost which is a function of its operating cost and its processing speed. The allocation is then optimized by transferring portions of the load from the expensive processors to the cheaper processor while maintaining an acceptable finish time for all processing. The optimization can also be performed for minimizing the finish time of the processors within a cost constraint.

Load sharing controller for optimizing monetary cost

Algorithms specified for parametrically sized problems are more general purpose and more reusable than algorithms for fixed sized problems For this reason, there is a need for representing and symbolically analyzing linearly parameterized algorithms An important class of parallel algorithms can be described as systems of parameterized affine recurrence equations (PARE) In this representation, linearly parameterized polyhedra are used to describe the domains of variables This paper describes an algorithm which computes the set of parameterized vertices of a polyhedron, given its representation as a system of parameterized inequalities This provides an important tool for the symbolic analysis of the parameterized domains used to define variables and computation domains in PAREs A library of operations on parameterized polyhedra based on the Polyhedral Library has been written in C and is freely distributed

Parameterized polyhedra and their vertices

Systems of linear recurrences are a very powerful means for specifying algorithms that need to be implemented on a systolic array or, more generally, on a parallel architecture. In particular, the class of linear recurrences called uniform recurrences can be mapped automatically on systolic arrays. However, it is often difficult to express the algorithm directly using strictly uniform recurrences, especially when the algorithm involves recursive computations, as in the transitive closure problem. Novel tools for the uniformization of linear recurrences are provided. Their use is illustrated by solving the so-called routing problem, which is a particular uniformization problem. Two routing strategies are presented, namely, hierarchical routing and split routing. >

Uniformization of linear recurrence equations: a step toward the automatic synthesis of systolic arrays

Loop transformations have been shown to be very useful in parallelising compilation and regular array design. This paper provides a solution to the open problem of automatic rewriting loop nests for non-unimodular transformations. We present an algorithm that rewrites a loop nest under any non-singular (unimodular or non-unimodular) transformation in a mechanical manner. The algorithm works nicely with unimodular transformations being treated as a special case. The extra time complexity incurred due to non-unimodularity is polynomially bounded by the depth of the loop nest.

Automating non-unimodular loop transformations for massive parallelism

The authors present a method for the mapping of systolic algorithms that use the minimal number of processors. This method is based on geometrical interpretations on convex polyhedra in Z/sup n/. The authors present a recurrence equation model defining the target problems for systolic program derivation. Some geometrical tools on convex polyhedra in Z/sup n/ are given. They are first used to model systolic timing allocation in terms of geometrical structures, and then to deduce a processor array mapping method that automatically gives space-optimal mappings. The results are used to derive two space-optimal mappings of the Gaussian elimination algorithm. >

Calculus of space-optimal mappings of systolic algorithms on processor arrays

We present a method for the synthesis of systolic arrays from a system of recurrent equations of a problem. The class of solved problems involves the inductive ones. For an inductive problem, the result sequence is calculated using its own elements : after its calculation, each element of this sequence is used as a data for other elements calculations. Therefore, the systolic arrays solutions are characterized by a ‘reinjection’ of each element of the result sequence in a data stream after its calculation.

Synthesis of systolic arrays for inductive problems

We propose a method based on geometrical tools to map problems onto regular and synchronous processor arrays. The problems we consider are defined by systems of affine recurrence equations (SARE). From such a problem specification we extract the data dependencies in terms of two classes of vectors: the utilization vectors and the dependence vectors. We use these vectors to express constraints on the timing or the allocation functions. We differentiate two classes of constraints. The causal ones are intrinsic timing constraints induced by the system of equations defining the problem. A given choice of target architecture may impose new constraints on the timing or the allocation. We call them the architecture-related constraints. We use these constraints to determine first an affine timing function and next an allocation by projection. We finally illustrate the method with three examples: the matrix multiplication, the recursive convolution and the LLt Cholesky factorization.

Geometrical tools to map systems of affine recurrence equations on regular arrays

The aim of this paper is to introduce a new modeling, using symbols and functional notations, called the language PEI (as Parallel Equations Interpretor), which could unify the classical approaches of program parallelization, according to the sorts of problems and the target computation schemes. Due to its fundamental structure, disconnected from concrete drawings, this modeling offers a straightforward generalization to adress convex or non-convex computation domains, synchronous or asynchronous computations. This sort of programming formalism allows a powerful structuration of statements and a stepwise tranformation technique based on a semantical equivalence definition and a refinement calculus. From initial problem statements, transformations of expressions lead to various definition structures, which can match given computation models.

PEI: A language and its refinement calculus for parallel programming☆

Synthesis of process arrays

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