The method of the current invention provides a fault tolerant access to a network resource. A replicated network directory database operates in conjunction with server resident processes to remap a network resource in the event of a server failure. The records/objects in the replicated database contain for each network resource, a primary and a secondary server affiliation. Initially, all users access a network resource through the server identified in the replicated database as being the primary server for the network resource. When server resident processes detect a failure of the primary server, the replicated database is updated to reflect the failure of the primary server, and to change the affiliation of the network resource from its primary to its backup server. This remapping occurs transparently to whichever user/client is accessing the network resource. As a result of the remapping, all users access the network resource through the server identified in the replicated database as the backup server for the resource. When the server resident processes detect a return to service of the primary server, the replicated database is again updated to reflect the resumed operation of the primary server. This remapping of network resource affiliations also occurs transparently to whichever user/client is accessing the network resource, and returns the resource to its original fault tolerant state.

Method for providing a fault tolerant network using distributed server processes to remap clustered network resources to other servers during server failure

A router (20) for switching data packets from a source (10) to a destination (30) in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks. Each memory bank is used for storing uniform portions of a data packet received from a source (10) and linking information for each data packets to allow for extraction of the uniform portions of a data packets from distributed locations in memory in proper order after a routing determination has been made by the router (20).

Memory organization in a switching device

A system for fault tolerant execution of an application program in a server network, which includes: a first server for executing the application program; a cluster network database, coupled to the first server; an object, stored in the cluster network database, which represents the program and contains information pertaining to the program; a failure detection module which detects a failure of the first server; a second server, coupled to the cluster network database; and a failover module which loads the application program in the second server upon detection of the failure of the first server. The information contained within the object includes: a host server attribute which identifies which server is currently executing the program; a primary server attribute which identifies which server is primarily responsible for executing the program; and a backup server attribute which identifies which server is a backup server for executing the program if the primary server experiences a failure.

System for clustering software applications

A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a management system by which computer users can accurately gauge the health of their computer. The network of microcontrollers provides users the ability to detect system fan speeds, internal temperatures and voltage levels. The invention is designed to not only be resilient to faults, but also allows for the system maintenance, modification, and growth—without downtime. Additionally, the present invention allows users to replace failed components, and add new functionality, such as new network interfaces, disk interface cards and storage, without impacting existing users. One of the primary roles of the present invention is to manage the environment without outside involvement. This self-management allows the system to continue to operate even though components have failed.

Diagnostic and managing distributed processor system

A software architecture for the hot add and swap of adapters. The software architecture allows users to replace failed components, upgrade outdated components, and add new functionality, such as new network interfaces, disk interface adapters and storage, without impacting existing users. The software architecture supports the hot add and swap of off-the-shelf adapters, including those adapters that are programmable.

Method for the hot swap of a mass storage adapter on a system including a statically loaded adapter driver

In a data processing system, an input output bus unit (IOBU) is connected one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous handshaking manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, message acceptance operation.

Method for transferring information between main store and input output bus units via a sequence of asynchronous bus and two synchronous buses

In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.

An input output interface controller connecting a synchronous bus to an asynchronous bus and methods for performing operations on the buses

Coupled synchronous-asychronous bus structure for transferring data between a plurality of peripheral input/output controllers and a main data store

Method for performing inter-unit data transfer operations among a plurality of input/output bus interface units coupled to a common asynchronous bus

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Method for transferring information between main store and input output bus units via a sequence of asynchronous bus and two synchronous buses

An input output interface controller connecting a synchronous bus to an asynchronous bus and methods for performing operations on the buses

Coupled synchronous-asychronous bus structure for transferring data between a plurality of peripheral input/output controllers and a main data store

Method for performing inter-unit data transfer operations among a plurality of input/output bus interface units coupled to a common asynchronous bus