Gregory Buehrer
Ohio State University
24 Papers
439 Citations
Gregory Buehrer is an academic researcher from Ohio State University. The author has contributed to research in topics: Scalability & Data stream mining. The author has an hindex of 12, co-authored 24 publications. Previous affiliations of Gregory Buehrer include Microsoft.
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Papers
Using parse tree validation to prevent SQL injection attacks
Gregory Buehrer,Bruce W. Weide,Paolo A. G. Sivilotti +2 more
- 05 Sep 2005
TL;DR: A technique to prevent this kind of manipulation and hence eliminate SQL injection vulnerabilities is described, based on comparing, at run time, the parse tree of the SQL statement before inclusion of user input with that resulting after inclusion of input.
•Proceedings Article
Cache-conscious frequent pattern mining on a modern processor
Amol Ghoting,Gregory Buehrer,Srinivasan Parthasarathy,Daehyun Kim,Anthony Nguyen,Yen-Kuang Chen,Pradeep Dubey +6 more
- 30 Aug 2005
TL;DR: A cache-conscious prefix tree is proposed to address poor data locality and low instruction level parallelism (ILP) in frequent pattern mining algorithms and improves spatial locality and also enhances the benefits from hardware cache line prefetching.
Cache-conscious frequent pattern mining on modern and emerging processors
Amol Ghoting,Gregory Buehrer,Srinivasan Parthasarathy,Daehyun Kim,Anthony Nguyen,Yen-Kuang Chen,Pradeep Dubey +6 more
- 25 Jan 2007
TL;DR: A cache-conscious prefix tree is proposed to address the problem of poor data locality and low instruction level parallelism on a modern processor by realizing a non-naive thread-based decomposition that targets simultaneously multi-threaded processors (SMT).
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Toward terabyte pattern mining: an architecture-conscious solution
Gregory Buehrer,Srinivasan Parthasarathy,Shirish Tatikonda,Tahsin Kurc,Joel H. Saltz +4 more
- 14 Mar 2007
TL;DR: The algorithm embraces the holistic notion of architecture-conscious datamining, taking into account the capabilities of the processor, the memory hierarchy and the available network interconnects, and results demonstrate that the proposed strategy result in near-linearscaleup on up to 48 nodes.
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Patent
Scheduling and partitioning tasks via architecture-aware feedback information
Aysel Ozgur,Gregory Buehrer,Anthony Nguyen,Daehyun Kim,Victor W. Lee,Mikhail Smelyanskiy,Yen-Kuang Chen +6 more
- 15 Dec 2005
TL;DR: In this article, the authors present a method for performing a first level task of an application in a first processor of a system and dynamically allocating a second level task to one of the first processor and a second processor based on architectural feedback information.
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