The ever increasing requirements for electrical performance of on-chip wiring has driven three major technological advances in recent years. First, copper has replaced Aluminum as the new interconnect metal of choice, forcing also the introduction of damascene processing. Second, alternatives for SiO2 with a lower dielectric constant are being developed and introduced in main stream processing. The many new resulting materials needs to be classified in terms of their materials characteristics, evaluated in terms of their properties, and tested for process compatibility. Third, in an attempt to lower the dielectric constant even more, porosity is being introduced into these new materials. The study of processes such as plasma interactions and swelling in liquid media now becomes critical. Furthermore, pore sealing and the deposition of a thin continuous copper diffusion barrier on a porous dielectric are of prime importance. This review is an attempt to give an overview of the classification, the character...

Low dielectric constant materials for microelectronics

Modern computer microprocessor chips are marvels of engineering complexity. For the current 45 nm technology node, there may be nearly a billion transistors on a chip barely 1 cm2 and more than 10 000 m of wiring connecting and powering these devices distributed over 9-10 wiring levels. This represents quite an advance from the first INTEL 4004B microprocessor chip introduced in 1971 with 10 μm minimum dimensions and 2 300 transistors on the chip! It has been disclosed that advanced microprocessor chips at the 32 nm node will have more than 2 billion transistors.1 For instance, Figure 1 shows a sectional 3D image of a 90 nm IBM microprocessor, containing several hundred million integrated devices and 10 levels of interconnect wiring, designated as the back-end-of-the-line (BEOL). Since the invention of microprocessors, the number of active devices on a chip has been exponentially increasing, approximately doubling every two years. This trend was first described in 1965 by Gordon Moore,2 although the original discussion suggested doubling the number of devices every year, and the phenomenon became popularly known as Moore’s Law. This progress has proven remarkably resilient and has persisted for more than 50 years. The enabler that has permitted these advances is known as scaling, that is, the reduction of minimum device dimensions by lithographic advances (photoresists, tooling, and process integration optimization) by ∼30% for each device generation.3 It allowed more active devices to be incorporated in a given area and improved the operating characteristics of the individual transistors. It should be emphasized that the earlier improvements in chip performance were achieved with very few changes in the materials used in the construction of the chips themselves. The increase of performance with scaling * Corresponding author. E-mail: gdubois@us.ibm.com. † IBM Almaden Research Center. ‡ Stanford University. Willi Volksen received his B.S. in Chemistry (magna cum laude) from New Mexico Institute of Mining and Technology in 1972 and his Ph.D. in Chemistry/Polymer Science from the University of Massachusetts, Lowell, in 1975. He then joined the research group of Prof. Harry Gray/Dr. Alan Rembaum at the California Institute of Technology as a postdoctoral fellow and upon completion of the one-year appointment joined Dr. Rembaum at the Jet Propulsion Laboratory as a Senior Chemist in 1976. In 1977 Dr. Volksen joined the IBM Research Division at the IBM Almaden Research Center in San Jose, CA, where he is an active research staff member in the Advanced Materials Group of the Science and Technology function.

Low dielectric constant materials.

Dense and porous hyperbranched carbosiloxane thin films (HBCSO) are obtained by sol-gel processing using methylene-bridged hyperbranched polycarbosilanes (HBPCSs) with the general compositional formula {(OMe) 2 Si(CH 2 )). Introduction of porosity is achieved using a porogen templating approach, allowing the control of the films' dielectric constant from 2.9 to as low as 1.8. Over the entire dielectric range, the HBCSO films exhibit exceptional mechanical properties, 2-3 times superior to those obtained for non-alkylene bridged organosiloxanes such as methylsilsesquioxanes (MSSQs) of similar densities and k-values.

Ultra Low‐k Films Derived from Hyperbranched Polycarbosilanes (HBPCS)

Plasma-based ashing of photoresist masks after pattern transfer is a common processing step in the fabrication of integrated circuits. In this work we investigated damage mechanisms of nanoporous ultra low k (ULK) materials with different overall porosities due to the ashing process. Oxygen-, nitrogen- and hydrogen-based photoresiststripping using direct and remote plasma processes were examined. Ellipsometry, x-ray photoelectron spectroscopy,secondary ion mass spectroscopy, and transmission electron microscopy were utilized to study the damage layer thickness, physical (pore morphology), and chemical modifications of the nanoporoussilica thin films after exposure to the O 2 -, N 2 - or H 2 -based ashing processes. As a result of the plasma exposure, carbon groups in nanoporoussilica can be removed from the ULK layers which is also accompanied by material densification. We find severe ashing damage of ULK materials after O 2 -based ashing using both direct and remote discharges. N 2 and H 2 discharges also damage ultralow k materials for direct plasma ashing processes which are accompanied by low energy ion bombardment of the substrates. The introduction rate and degree of the ULK materials modifications correlates with the overall porosity. We show that the pore interconnectivity is one of the key parameters that determine ashing damage. ULK damage is greatly reduced for remote N 2 or H 2 discharges, but the resist removal rates are impractically low if the substrate is at room temperature. We show that both acceptable photoresist stripping rates and ULK damage levels can be achieved for remote H 2 plasma ashing processes if the substrate temperature is 250 ° C and higher.

Damage of ultralow k materials during photoresist mask stripping process

The increasing sensitivity of porous low dielectric constant materials to process damage constitutes a major roadblock to their implementation in back-end-of-the-line (BEOL) wiring structures for advanced technology nodes. In the early 2000s and in anticipation to future low-k related integration challenges, the semiconductor industry started to investigate the possibility to repair or prevent this damage. It is remarkable that the most disruptive solutions proposed today are inspired from the work initiated more than 10 years ago. In this review we first describe the accepted mechanisms for plasma damage, followed by a quick summary of the methods used to quantify its extent on both blanket films and patterned structures. We then report on the past and current strategies developed to mitigate the plasma damage of porous, low-k materials during damascene integration processes.

JSS FOCUS ISSUE ON ADVANCED INTERCONNECTS :M ATERIALS ,P ROCESSING, AND RELIABILITY Toward Successful Integration of Porous Low-k Materials: Strategies Addressing Plasma Damage

Dependence of the minimal PVD TA(N) sealing thickness on the porosity of Zirkon TM LK Dielectric films

Comparison of modulus and density measurements by nanoidentation, SAWS, XRR and EP techniques of a porous low k MSQ dielectric

3D IC integration based on TSV technology has been recognized as a key enabler for next generation of electronic devices with reduced size factor and improved performances. The adoption of 3D-TSV technology also requires the development of innovative interconnect solutions that reduces the size of signal routing and therefore imposes new demands on dielectric materials used to isolate the copper interconnects. Benzocyclobutene polymers (Dow's CYCLOTENE™ Advanced Electronic Resins) have been used to isolate copper interconnects in packaging applications for more than 20 years, due to a number of good attributes of the BCB polymer including low copper drift rate, low dielectric constant and low loss, low moisture absorption and proven reliability. However, the low fracture toughness and low elongation of BCB polymer has limited its use in stress buffer applications due to solder bump failure. Here we report the development of new laser and photodefinable toughened benzocyclobutene (BCB) dielectric materials...

Development of Laser and Photodefinable Toughened Benzocyclobutene Dielectric Materials for 3D-TSV Integration

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Dependence of the minimal PVD TA(N) sealing thickness on the porosity of Zirkon TM LK Dielectric films

Comparison of modulus and density measurements by nanoidentation, SAWS, XRR and EP techniques of a porous low k MSQ dielectric

Development of Laser and Photodefinable Toughened Benzocyclobutene Dielectric Materials for 3D-TSV Integration