Giovanny Sanchez
Instituto Politécnico Nacional
31 Papers
59 Citations
Giovanny Sanchez is an academic researcher from Instituto Politécnico Nacional. The author has contributed to research in topics: Computer science & Neuromorphic engineering. The author has an hindex of 5, co-authored 18 publications.
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Papers
SNAVA-A real-time multi-FPGA multi-model spiking neural network simulation architecture.
T. A. Athul Sripad,Giovanny Sanchez,Mireya Zapata,Vito Pirrone,Taho Dorta,Salvatore Cambria,Albert Martí,Karthikeyan Krishnamourthy,Jordi Madrenas +8 more
TL;DR: This contribution intends to provide a tool that allows to prototype SNNs faster than on CPU/GPU architectures but significantly cheaper than fabricating a customized neuromorphic chip.
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Aer-srt
TL;DR: The AER-SRT (Address Event Representation over Synchronous Serial Ring Topology) as mentioned in this paper is a packet-based solution implemented with high-speed serial link for multi-chip SNN communication.
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Small universal spiking neural P systems with dendritic/axonal delays and dendritic trunk/feedback
Luis Garcia,Giovanny Sanchez,Eduardo Vazquez,Gerardo Avalos,Esteban Anides,Mariko Nakano,Gabriel Sánchez,Hector Perez +7 more
TL;DR: In this article, a new variant of the spiking neural P (SN P) system with dendritic and axonal computation (DACSN P system) is presented, which includes experimentally proven biological features in the current SN P systems to reduce the computational complexity of the soma by providing it with stable firing patterns.
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A highly scalable parallel spike-based digital neuromorphic architecture for high-order fir filters using LMS adaptive algorithm
Giovanny Sanchez,Carlos Díaz,Juan-Gerardo Avalos,Luis Garcia,Angel Vazquez,Karina Toscano,Juan-Carlos Sanchez,Hector Perez +7 more
TL;DR: The results demonstrate that the neuromorphic architecture is capable of processing higher adaptive FIR filters compared with previously reported solutions and potentially allow its practical use in many advanced digital signal processing applications such as acoustic echo cancellers, active noise control, channel equalization and system identification.
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A new scalable parallel adder based on spiking neural P systems, dendritic behavior, rules on the synapses and astrocyte-like control to compute multiple signed numbers
Thania Frias,Giovanny Sanchez,Luis Garcia,Marco Abarca,Carlos Díaz,Gabriel Sánchez,Hector Perez +6 more
TL;DR: The results show that the implementation on a low-area low-cost FPGA requires small amount of circuitry, which potentially allows the development of highly parallel architectures that can be used in advanced applications, such as portable mobile robots, mobile devices, image and vision processing, among others.
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