The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.

System and method for handling load and/or store operations in a superscalar microprocessor

A reduced instruction set computer (RISC) with a Harvard architecture is disclosed. The RISC may be designed to be used simply as a RISC or may be designed to be used to emulate a complex instruction set computer (CISC). Or, it may be designed for use as either. A CISC design methodology is disclosed whereby a RISC is designed and fabricated and whereby RISC emulation code is written concurrently with design and fabrication and also subsequent to fabrication.

Reduced instruction set computing apparatus and methods

A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer

A lookup mechanism provides an input value to a datapath element disposed in an execution datapath of a processor and causes the datapath element to compare the input value to stored identifier values. The lookup mechanism receives from the datapath element a result based on the comparison.

A software controlled content addressable memory in a general purpose execution datapath

In a RISC device a set of four instructions are provided which allow either the loading or the storage of an unaligned reference. The instructions are overlapped to reduce the overall execution time of the device. A circuit is also provided for executing the instruction set.

Risc computer with unaligned reference handling and method for the same

A mechanism for performing fast and efficient full shift, merge, insert and bit alignment functions within one operating machine cycle of a host primitive instructions set computing system. In general, the circuitry performs a ring shift under control of a mask. The circuitry further combines essentially parallel rotate and mask and merge functions all executable in one machine cycle. The circuitry further allows the provision of powerful bit, digit, and bit rotate with mask instructions which are particularly useful primitive operations for decimal packing and unpacking functions as well as for implementing floating point preshifting and normalization functions.

Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system

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Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system