Georg Post
Bell Labs
18 Papers
38 Citations
Georg Post is an academic researcher from Bell Labs. The author has contributed to research in topics: Network packet & Traffic generation model. The author has an hindex of 4, co-authored 18 publications. Previous affiliations of Georg Post include Alcatel-Lucent.
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Papers
Semantic networking: Flow-based, traffic-aware, and self-managed networking
Ludovic Noirie,Emmanuel Dotaro,Giovanna Carofiglio,Arnaud Dupas,Pascal Pecci,Daniel Popa,Georg Post +6 more
TL;DR: This work introduces a new paradigm of semantic networking for the networks of the future, which brings together flow-based networking, traffic awareness, and self-management concepts to deliver plug-and-play networks.
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Passive online RTT estimation for flow-aware routers using one-way traffic
Damiano Carra,Konstantin Avrachenkov,Sara Alouf,Alberto Blanc,Philippe Nain,Georg Post +5 more
- 11 May 2010
TL;DR: This work provides an online RTT estimation algorithm which is passive and needs one-way traffic only and tests on a controlled testbed and on the Internet demonstrate high accuracy of the proposed estimator.
Patent
Packet switching system for a communication network node
Ludovic Noirie,Silvio Cucchi,Georg Post +2 more
- 22 Dec 2004
TL;DR: In this article, the authors propose a switching system consisting of input modules (IM 1, IM 2, IMi, IMn) each connected to a switching matrix and corresponding controller (2).
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From Packets to XLFrames: Sand and Rocks for Transfer of Mice and Elephants
Dinil Mon Divakaran,Eitan Altman,Georg Post,Ludovic Noirie,Pascale Vicat-Blanc Primet +4 more
- 19 Apr 2009
TL;DR: The effects of introducing XLFs in a network are analysed, and the amount of packet-header processing is greatly reduced, while the fair multiplexing of XLFs with standard packets can be achieved using a careful queue management in routers.
Patent
Packet communication system within a communication network node
Silvio Cucchi,Ludovic Noirie,Georg Post +2 more
- 20 Dec 2004
TL;DR: In this paper, the system has input modules (IM1-IMn), each connected to a switching matrix (1) and a controller (2), each module has processing units for organizing packets into digital data blocks and for transferring the blocks towards the matrix.
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