Georg Hofferek
Graz University of Technology
20 Papers
159 Citations
Georg Hofferek is an academic researcher from Graz University of Technology. The author has contributed to research in topics: Formal specification & Debugging. The author has an hindex of 11, co-authored 20 publications.
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Papers
RATSY – a new requirements analysis tool with synthesis
Roderick Bloem,Alessandro Cimatti,Karin Greimel,Georg Hofferek,Robert Könighofer,Marco Roveri,Viktor Schuppan,Richard Seeber +7 more
- 15 Jul 2010
TL;DR: RATSY is presented, a successor of the Requirements Analysis Tool RAT that includes a new graphical user interface to specify system properties as simple Buchi word automata and allows correct-by-construction synthesis of systems from their temporal properties.
Synthesizing robust systems
Roderick Bloem,Krishnendu Chatterjee,Karin Greimel,Thomas A. Henzinger,Georg Hofferek,Barbara Jobstmann,Bettina Könighofer,Robert Könighofer +7 more
TL;DR: This article defines two robustness notions, combine them, and shows how to enforce them in synthesis of robust reactive systems from temporal specifications, and presents an implementation of a special case of robustness.
114
Debugging formal specifications using simple counterstrategies
Robert Könighofer,Georg Hofferek,Roderick Bloem +2 more
- 11 Dec 2009
TL;DR: This work shows that it can explain conflicts with the design intent by explaining unrealizability, and proposes a debugging method for incorrect specifications that does not need an implementation.
73
Debugging formal specifications: a practical approach using model-based diagnosis and counterstrategies
TL;DR: This work presents the countertrace or the counterstrategy as an interactive game against the user, and as a graph summarizing possible plays of this game, where it is shown how model-based diagnosis can be applied to locate an error in an unrealizable specification.
71
•Proceedings Article
Symbolically synthesizing small circuits
Rüdiger Ehlers,Robert Kunighofer,Georg Hofferek +2 more
- 01 Oct 2012
TL;DR: This paper proposes implementation-extraction based on computational learning of Boolean functions as a final synthesis step in order to obtain small and fast circuits for realizable specifications in a symbolic way.