This paper analyzes the dynamic power consumption in the fabric of Field Programmable Gate Arrays (FPGAs) by taking advantage of both simulation and measurement. Our target device is Xilinx Virtex™-II family, which contains the most recent and largest programmable fabric. We identify important resources in the FPGA architecture and obtain their utilization, using a large set of real designs. Then, using a number of representative case studies we calculate the switching activity corresponding to each resource. Finally, we combine effective capacitance of each resource with its utilization and switching activity to estimate its share of power consumption. According to our results, the power dissipation share of routing, logic and clocking resources are 60%, 16%, and 14%, respectively. Also, we concluded that dynamic power dissipation of a Virtex-II CLB is 5.9mW per MHz for typical designs, but it may vary significantly depending on the switching activity.

/pdf/dynamic-power-consumption-in-virtex-ii-fpga-family-3ukdpccroz.pdf

Dynamic power consumption in Virtex™-II FPGA family

From the Publisher:
* Practical approach to design
* Case studies allow the readers to investigate their own systems
* The author, Steve Heath, has many years' experience in computer design

Microprocessors are more and more present in many aspects of our daily lives. They have become the standard way of implementing digital systems ranging from sophisticated process control systems to cars, burglar alarms and even children's toys. As a result, the demand for these products is increasing dramatically, as is the need for knowledge and understanding of the technology. 
This book provides a guide to all aspects of embedded systems design including the hardware, software and the design trade-offs associated with design. The approach taken here is largely practical, the aim being to explain how systems are designed in the real world rather than in theory. In keeping with this approach, there is a chapter of case studies included in the book to allow the readers to investigate their own real systems and gain practical experience.

Embedded Systems Design

Simultaneous Dynamical Integration modeling techniques are applied to placement of elements of integrated circuits as described by netlists specifying interconnection of devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node populations. The forces are optionally selectively modulated as a function of simulation time. The placements of the devices are compatible with various design flows, such as standard cell, structured array, gate array, and field-programmable gate array.

Methods and systems for placement

Power has become a critical issue for field-programmable gate array (FPGA) vendors. Understanding the power dissipation within FPGAs is the first step in developing power-efficient architectures and computer-aided design (CAD) tools for FPGAs. This article describes a detailed and flexible power model which has been integrated in the widely used Versatile Place and Route (VPR) CAD tool. This power model estimates the dynamic, short-circuit, and leakage power consumed by FPGAs. It is the first flexible power model developed to evaluate architectural tradeoffs and the efficiency of power-aware CAD tools for a variety of FPGA architectures, and is freely available for noncommercial use. The model is flexible, in that it can estimate the power for a wide variety of FPGA architectures, and it is fast, in that it does not require extensive simulation, meaning it can be used to explore a large architectural space. We show how the model can be used to investigate the impact of various architectural parameters on the energy consumed by the FPGA, focusing on the segment length, switch block topology, lookuptable size, and cluster size.

/pdf/a-detailed-power-model-for-field-programmable-gate-arrays-ouqr536por.pdf

A detailed power model for field-programmable gate arrays

We consider active leakage power dissipation in FPGAs and present a "no cost" approach for active leakage reduction. It is well-known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs. Our leakage reduction technique leverages a fundamental property of basic FPGA logic elements (look-up-tables) that allows a logic signal in an FPGA design to be interchanged with its complemented form without any area or delay penalty. We apply this property to select polarities for logic signals so that FPGA hardware structures spend the majority of time in low leakage states. In an experimental study, we optimize active leakage power in circuits mapped into a state-of-the-art 90nm commercial FPGA. Results show that the proposed approach reduces active leakage by 25%, on average.

/pdf/active-leakage-power-optimization-for-fpgas-2nyhwa3ja5.pdf

Active leakage power optimization for FPGAs

2011 Gary K Yeap Practical Low Power Digital Vlsi Design April 21st, 2019 c1731006c4 FPGA Architectures amp Applications Testing amp Testability Low Power VLSI Design 2002 kluwer academic publishers Gary K Yeap Practical Low Power Digital Neil Weste and K Eshragian Principles of CMOS VLSI Design A PRACTICAL LOW POWER DIGITAL VLSI DESIGN Springer April 10th, 2019 ceived when I developed a company wide training class Tutorial on Low Power Digital VLSI Design for designers in Motorola The feedback from the tutorial attendees helps to

Practical Low Power Digital VLSI Design

The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Topo-clusters may be formed based on various criteria including, for example, functional similarity, proximity (in terms of number of nets), and genus. Genus refers to a representation of a netlist in terms of a number of planar netlists—netlists in which no crossing of nets occurs. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. The portion of a topo-cluster placed within a given bin is called a quanto-cluster. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM), and in particular Dual GBFM. In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics—delay, area, congestion, power, etc. “Dual” refers to the fact that each iteration has two phases. During a first phase, FM is performed within a region on a quanto-cluster basis. During a second phase, FM is performed within the region on a gate basis. GBFM occurs in the context of recursive quadrisection. Hence, after GBFM has been completed, a further quadrisection step is performed in which each bin is divided into four bins, with a quarter of the gates of the original bin being placed in the center of each of the resulting bins. GBFM then follows, and the cycle repeats until each bin contains a fairly small number of gates. Following the foregoing global placement process, the circuit is then ready for detailed placement in which cells are assigned to placement rows.

Placement method for integrated circuit design using topo-clustering

A design tool for integrated circuits includes a placement tool which places logic gates and interconnect components concurrently. Probabilistic interconnect models are used to represent the collection of possible interconnect routings that provide acceptable circuit performance and routing area.

System and method for concurrent placement of gates and associated wiring

We address the problem of state encoding for synchronous finite state machines (FSM's), targeted for low power design. Most previous work in FSM state encoding has been focused on minimizing chip area and does not consider switching activity of the circuit. As a result, this does not always lead to a power efficient implementation. Especially in CMOS circuits, the switching activity is a very important factor in power dissipation. In this work, we define a function /spl lambda/ for automatic tradeoff between switching activity and area that contribute to power dissipation. /spl lambda/ is used in determining the encoding affinity between states and is observed to be related to the number of states of a FSM in our experiments. A state encoding algorithm, based on hypercube embedding, is proposed to find encodings of states such that the sum of bit toggles between each pair of states times the encoding affinity between them is minimized. Results over a wide range of MCNC benchmark examples which show the efficacy of our technique are presented.

State encoding of finite state machines for low power design

This invention recognizes the ability of logic optimization to help placement relieve congestion. Different types of logic optimizations are used to help placement relieve congestion. In one type of optimization, the speed of parts of the circuit is improved by selecting faster cells. In another type of optimization, the topology of the circuit is changed such that placement can now move cells, which could not have been moved before, to reduce congestion and thus enable routing. A distinguishing feature of this methodology is that it not only uses the placement information for interconnection delay/area estimates during logic optimization, but also uses logic optimization to aid the physical placement steps by providing support to placement so that the congestion of the circuit is improved. The aim is to avoid getting into a situation where the placed circuit cannot be routed.

Method for logic optimization for improving timing and congestion during placement in integrated circuit design

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

Gary Yeap

Author Tools

Chat about Author