Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity (<1 mm separation) compared with several centim...

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Heterogeneous 2.5D integration on through silicon interposer

With the size of transistors scaling down, 3D IC packaging emerged as one of the most promising solutions to achieve system integration on the track of Moore's Law. In this article, we demonstrated a sub-system with one 28nm logic device and two 40nm chips on a 600mm2 silicon interposer with Through-Silicon-Via (TSV) integrating 4 layers of high density interconnects. The packages were assembled using our proprietary CoWoS (Chip on Wafer on Substrate) technology that incorporated 270,000 micro-bump (μBump) and 8,700 C4 bumps. Comprehensive reliability characterization and test methods will be presented. It includes copper interconnect reliability of silicon interposer on EM, SM and IMD TDDB with the presence of TSV. μBump EM and TSV EM are characterized to provide a design guideline for maximum current carrying capability; the EM test methodology was also used to optimize the integrated process, e.g. TSV copper plating, μBump joint, and interface treatment of TSV revealing. Package process optimization, bill of material selectio n and qualificatio n we r e conducted on a 28nm Cu/ELK (Extreme low-K) test vehicle taking Chip-Package-Interaction into consideration. Not only component level package reliability tests were performed, board level Thermal Cycling, Power Cycling and Mechanical Shock tests were also executed to understand the reliability margin and potential failure modes in field use condition. The typical failure modes and mechanisms will be discussed. CoWoS technology is eventually successfully developed with enhanced reliability. The results highlight the importance of a highly integrated 3D IC technology from silicon wafer process to assembly packaging. This work shows that in the new paradigm of 3D IC integration, Si Foundry is positioned at a unique leadership to manage the innovation in Si processes and the improvement of Si assembly operating life.

Reliability characterization of Chip-on-Wafer-on-Substrate (CoWoS) 3D IC integration technology

In this investigation, a system-in-package (SiP) that consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top and bottom sides (a real 3-D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top chip, bottom chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be performed to demonstrate the integrity of the SiP structure.

Through-Silicon Hole Interposers for 3-D IC Integration

Advanced packaging for high end field programmable gate array (FPGA) applications, such as data center and emulation, has recently focused on silicon interposers to enable higher transistor counts and increasing bandwidth, leading to increased power and larger packages, up to 55 mm x 55 mm. The increasing complexity, larger package size, and smaller pitches which enable these advancements pose mechanical challenges such as warpage and reliability. To accommodate the increased power, a stiffener ring may replace the lid. High bandwidth memory (HBM) offers significant performance gain in the form of a vertical stack of memory chips. However, the use of a stiffener ring and incorporation of HBM exacerbate the warpage and reliability challenges, especially as package sizes continue to increase. This work studies the design constraints upon these large packages and to find that reliable packages may be achieved. This work starts by introducing the current options for advanced packaging of an FPGA. The 2.5D silicon interposer structure was selected and the current structure for an FPGA was designed, fabricated, and tested. Warpage was measured with DIC, -40 to 125 °C thermal cycling reliability tests were conducted through 1200 cycles, and high temperature storage tests at 150 °C were conducted for 2000 hours. Through these reliability experiments, the primary mechanical challenges associated with the design space were identified to be thermal cycling and warpage. Finite element models were built and validated using warpage data. Design parameters including ring material, ring size, and substrate CTE were analyzed for their effect on warpage and reliability. Then, a second design was created by optimizing tradeoffs to meet the warpage requirement and improve reliability as much as possible. The second design passed all warpage and reliability requirements.

Warpage and Reliability Challenges for Stacked Silicon Interconnect Technology in Large Packages

In this work the effects of 3D stacking technology on the performance of devices are systematically studied. For this study a special chip consisting of a number of stress sensors and vertical interconnect loops was designed and manufactured in 65 nm technology. Local variations of stress with a magnitude of up to 300 MPa are detected at different locations along the chip and are being characterized using finite element modeling and micro-Raman spectroscopy measurements.

3D stacking induced mechanical stress effects

In this paper, an advanced 40nm, Cu/low-K 22×18mm2 Si chip with 42.5×42.5mm2 flip chip BGA-1681L package was used with substrate core material split on CTE ∼12ppm vs. 17ppm, and underfill material split on high Tg vs. low Tg. The packages were mounted on PWB (printed wiring board) for second-level interconnect SAC405 BGA reliability characterization. Thermal heaters and sensors were built-in the chip with first-level and second-level interconnect daisy chain designs to enable power cycling and thermal cycling reliability characterization. Experiments with variety of temperature range were conducted to compare second-level interconnects reliability under power cycling and thermal cycling tests. The results showed that thermal cycling with 25∼125°C profile could accelerate the test compared with 0∼100°C and reflected the similar failure ball location in the die-shadow edge as that from power cycling test. However, the typical thermal cycling ranging between 0°C and 100°C showed different worst cracked balls location around the package edge. An acceleration stress methodology for second-level interconnects reliability had been established on power cycling by increasing temperature ramp rate and raising peak temperature, while still keeping the same failure phenomenon. Underfill Tg effect was observed on solder fatigue performance that high Tg underfill resulted in shorter fatigue cycle. Failure analysis was performed to understand the failure mode and failure location differences. A non-linear 3D board-level finite-element analysis (FEA) was carried out to characterize the second-level interconnect BGA strain distribution difference under power cycling and thermal cycling tests with underfill and substrate core material splits.

Second-level interconnects reliability for large-die flip chip lead-free BGA package in power cycling and thermal cycling tests

In this paper, a novel power cycling system with thermal test vehicle design following the concept defined in JESD22-A122 standard has been established to better approximate field operating conditions. The test unit used in the system is to simulate real product, therefore it is not only package on board but also with an external fan. A closed-loop controller with power modules in this system is able to activate thermal test chip and external fan for power cycling heating and cooling profile tracking, in parallel data acquisition can monitor in-situ daisy chain resistance. In addition, this system is designed to perform power cycling test on multi-packages, which is beneficial to characterize power cycling reliability in chip-to-package and package-to-system level integration and product performance during technology development. An advanced Cu/low-K 16×14mm2 silicon chip with 35×35mm2 −1156L lead free bump flip chip BGA package was used with underfill material splits on pairing low, medium, and high Tg and modulus values. The effect of underfill properties (Tg, modulus) on SnAg lead free bump flip chip package power cycling reliability was characterized and verified by FEM (finite element method). Besides, the power cycling profile temperature range and temperature ramp rate effect was discussed and quantified by weibull analysis. The results can provide useful guideline for chip to package integration even system design for further reliability enhancement.

Flip chip power cycling system development and lead free bump power cycling reliability

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Reliability characterization of Chip-on-Wafer-on-Substrate (CoWoS) 3D IC integration technology

Second-level interconnects reliability for large-die flip chip lead-free BGA package in power cycling and thermal cycling tests

Flip chip power cycling system development and lead free bump power cycling reliability