In this paper, bond via array (BVA) wirebond is used to achieve compact vertical integration and improve the electrical performance for system in package (SiP). Two techniques are presented. In the first technique, BVA wirebonds are utilized to integrate some passive or active components vertically onto other components. This significantly reduces the horizontal footprint of the entire SiP. In terms of electrical performance, this vertical integration provides much lower parasitic inductance than conventional 2-D horizontal integration design because of shorter interconnection. For example, the proposed technology can significantly reduce power delivery network impedance compared to a conventional design. In the second technique, we propose BVA wirebond wires as an electromagnetic interference (EMI) shield between different domains within SiP. This provides a lower cost solution for EMI shielding, particularly when regions within a package need to be shielded.

Improvements of System-in-Package Integration and Electrical Performance Using BVA Wire Bonding

This paper introduces a novel transmission line structure that can be employed in high-speed high-density copper interconnects, including both cables and connectors. The proposed structure uses a unique combination of dielectric materials with high and low permittivity values to decouple metal shields from adjacent signal pairs. In addition, the proposed structure employs an absorbing material to suppress any crosstalk resonances that may arise due to signal discontinuities in such highly dense environments. The optimum electrical properties of such an absorbing material in the proposed structure were determined using a simulation-based investigation. This paper also presents measured electrical properties of stereolithography resins suitable for rapid prototyping of high-speed interconnects. The effects of increasing the height of a connector on signal crosstalk and introducing any absorbing materials on signal loss are also discussed. Finally, this paper presents test boards and corresponding prototypes that were modeled and measured to validate the proposed transmission line structure for frequencies up to 40 GHz.

A Novel Transmission Line Structure for High-Speed High-Density Copper Interconnects

This paper presents a periodic electromagnetic bandgap (EBG) structure in the integrated fan-out wafer-level package (InFO-WLP) technology for gigahertz-band noise suppression. The proposed EBG structure consists of an $LC$ resonator with two symmetrical spiral inductors in series and a shunt metal–insulator–metal capacitor between power and ground planes. The third-order equivalent model of the EBG structure is also proposed and extracted by field solver ANSYS Q3D to model the performance. In addition, the EBG arrays with different sizes of unit cell and the corresponding stopband bandwidth and isolation were characterized. The measurement results show that the proposed $1 \times 4$ EBG array of 600- $\mu \text{m}$ square unit cell can achieve a 29.5-GHz stopband bandwidth together with an over 30-dB isolation level. Furthermore, by using the InFO-WLP technology, the proposed EBG structure is integrated with an RF low-noise amplifier (LNA) fabricated in a 16-nm FinFET technology as a case study to validate the power noise immunity. The experimental results show that the measured output spectrum of LNA integrated with the proposed EBG structure at the power plane can suppress the noise tone from −37.37 to −68.65 dBm.

An Electromagnetic Bandgap Structure Integrated With RF LNA Using Integrated Fan-Out Wafer-Level Package for Gigahertz Noise Suppression

In this paper, we propose and investigate two novel applications of absorbing materials to suppress high-frequency couplings in high-speed interconnects. In the first application, absorbing materials are added to connector housing to reduce the noises caused by crosstalk and resonances. In the second application, a low-emission inductor is proposed by applying absorbing materials surrounding the body of an inductor. Full-wave simulations and measurements are performed to verify the proposed techniques. Results show absorbing materials significantly improve the performance of signal/power integrity and greatly reduce electromagnetic interference for high-speed digital system designs.

Suppression of Couplings in High-Speed Interconnects Using Absorbing Materials

Maintaining low and smooth impedance over a wide range of frequency is one of the main issues in designing high-speed digital systems or mixed signal integrated circuits Cavity resonances of a printed circuit board coupled with discontinuous return current paths, series inductance of the power distribution network, and parasitic inductance make potentials at power/ground planes unstable One possible solution to improve power integrity and electromagnetic interference is to utilize a magnetodielectric absorber on the perimeter of the board A mode-matching method and an impedance boundary condition are employed to obtain a computationally inexpensive model of the system A contour plot of transfer impedance versus normalized surface impedance is introduced to provide useful information for determining the most suitable absorber Numerical and measurement results are discussed The results from the proposed modeling agree with those from the measurement and the simulation The selected absorber effectively reduces selfimpedance and transfer impedance at resonant frequencies, but resonances are not completely eliminated at low frequencies due to the low loss of the absorber

Improving Power Integrity by Using Magnetodielectric Absorbers Along the Perimeters of Printed Circuit Boards

Cavity Resonant Edge Effects (CREE) in printed circuit boards (PCBs) and packages can cause severe power integrity (PI) and electromagnetic interference/compatibility (EMI/EMC) issues. Electromagnetic radiation from PCB edges are major sources of EMI/EMC problems in electronic devices. Power supply noise, in the form of fast changing currents (di/dt), traverses the power-return paths of PCBs and packages using power vias. CREE produces considerable level of noise along the edges of PCB and package power planes due to signal coupling between vias and reflection along PCB edges with transient currents. In this paper, we investigate an approach to minimize cavity resonant noise by placing absorbing material along the edges of a PCB board. The upper peak (anti-resonant) impedance of the power distribution network (PDN) is reduced significantly. In this paper the simulated example shows the absorbing material reduces the upper impedance peaks as much as to 8% comparing to the impedance peaks without absorption material. Conclusively, the results show that adding absorbing material along the PCB edges significantly improves the noise issues by suppressing CREE.

Suppression of Cavity Resonant Edge Effects and PDN impedance using absorbing material

Apparatuses and methods associated with shield lines, and/or complementary decoupling capacitors and/or electromagnetic absorbing materials are disclosed herein. In embodiments, an apparatus may include a substrate having a ground plane; and a first and a second transmission line disposed on the substrate. Further, the apparatus may include a shield line constituted with electromagnetic absorbing material disposed between the first and second transmission lines and not coupled with the ground plane. In embodiments, the substrate may further include a power plane having a plurality of edges and a plurality of spacing; a plurality of decoupling capacitors disposed on the power or ground plane; and electromagnetic absorbing materials adhered to the plurality of edges and disposed in the plurality of spacing. Other embodiments may be described and/or claimed.

Crosstalk, power supply noise and/or emi reduction methods and apparatuses

In this paper, we present an approach to reduce the cavity resonant edge effects in printed circuit boards (PCBs) and semiconductor packages. Power supply noise, in the form of fast changing currents (di/dt), traverses the power-return paths of PCBs and semiconductor packages using power vias. The cavity effects produce considerable level of noise along the edges of PCB and integrated circuit (IC) package power planes due to signal coupling between vias and reflection from PCB edges with transient currents. The cavity effects also amplify the electromagnetic radiation from PCB edges, which are major sources of EMI/EMC problems in electronic devices. By using absorbing material and decoupling capacitors (de-caps) on power distribution networks (PDNs), we observe considerable mitigation in impedance noise, signal noise and electromagnetic interference/compatibility (EMI/EMC) issues caused by the cavity effects. In particular, simulation results show notable reduction of upper peak (anti-resonant) impedance noise and reduction in radiated emissions by as much as 20 dB. This article presents a comparative case-study using various models (Section 3) and report on their effectiveness to reduce the cavity effects. The models are listed as (1) “Original” model, (2) “Absorbing material along the edge” model, (3) “MURATA based De-cap only” model and (4) “Absorbing material along the edge w/De-cap” model. The used capacitance ranges between 0.1 μF and 22 μF. The ESR and ESL range between 2mOhm–20 mOhm and 238 pH–368 pH, respectively. Conclusively, we learn by adding absorbing material along the PCB edges with a few decoupling capacitors. The PDN impedance noise is improved, and EMI issues in PCBs and semiconductor packages suppress the cavity effects.

/pdf/reduction-of-pcb-pdn-impedance-and-radiated-emissions-using-mr4idlwdfo.pdf

Reduction of PCB PDN Impedance and Radiated Emissions Using a Hybrid Technique with Absorbing Materials and Decoupling Capacitors

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Papers

Suppression of Cavity Resonant Edge Effects and PDN impedance using absorbing material

Crosstalk, power supply noise and/or emi reduction methods and apparatuses

Reduction of PCB PDN Impedance and Radiated Emissions Using a Hybrid Technique with Absorbing Materials and Decoupling Capacitors