Garima Gill

TL;DR: In this paper , a novel compact model to capture the double-hump characteristic in the substrate current versus gate voltage plot of a high-voltage device is discussed, and an analytical expression for the electric field is derived by solving Poisson's equation at the drift-drain junction of the device, which is then incorporated in the final substrate current equation.

TL;DR: In this article , a parameter extraction methodology for the BSIM industry standard high-voltage (HV) device compact model is presented, which covers entire range of operation, including weak inversion to strong inversion region, low and high drain biases, and multiple body biases with temperature effects.

TL;DR: Improved compact model for LDMOS transistors over a wide temperature range including cryogenics. Includes carrier freeze-out, field-assisted ionization, and improved temperature dependence models.

TL;DR: This is the very first effort to use neural network of any sorts for on-chip deterministic test generation and uses binary encoded convolutional neural networks and using binary recurrent neural network as output compactor.