Algorithms for performing divisions over Z p and GF(p m ) are described, the corresponding digital circuits are synthesized and conclusions about their computation times are drawn. The results of their implementation within field-programmable devices are given in the case of the most efficient ones.

Hardware Implementation of Finite-Field Division

In this paper, we present a specific algorithm for the blind identification of a two input two output system. A closed form solution for the blind identification of the system is derived by exploiting the temporal coherence properties of the input sources. By exploiting the inherent indeterminacies of the blind processing, a simplified version is derived making the algorithm computationally cheaper and more suitable for hardware implementation. The weights of the zero forcing blind separator are then deduced. The performance of the proposed solutions with respect to the signal to noise ratio (SNR) and sample size are provided in the simulation section.

A closed form solution for the blind separation of two sources from two sensors using second order statistics

http://www.sersc.org/journals/IJSIA/vol10_no9_2016/12.pdf

Fast Hardware Implementations of Inversions in Small Finite Fields for Special Irreducible Polynomials on FPGAs

In this paper, we present a hardware implementation of a blind source separation algorithm having two input, two output, which uses a closed form solution by exploiting the temporal coherence properties of the input sources and the inherent indeterminacies of the blind processing. The proposed implementation is free division version, computationally cheaper and efficient for a hardware implementation. In addition, we propose an on-line block processing source separation environment that supports the implementation of the algorithm under consideration. We demonstrate the effectiveness of our implementation by providing its performance with respect to word length and sample size.

Hardware implementation of free division block-based BSS algorithm

Cryptographic protocols are implemented in hardware to ensure low-area, high speed and reduced power consumption especially for mobile devices. Elliptic Curve Cryptography (ECC) is the most commonly used public-key cryptosystem and its performance depends heavily on efficient finite field arithmetic hardware. Finding the multiplicative inverse (inversion) is the most expensive finite field operation in ECC. The two predominant algorithms for computing finite field inversion are Fermat’s Little Theorem (FLT) and Extended Euclidean Algorithm (EEA). EEA is reported to be the most efficient inversion algorithm in terms of performance and power consumption. This dissertation presents a new reformulation of EEA algorithm, which allows for speedup and optimization techniques such as concurrency and resource sharing. Modular arithmetic operations over GF(p) are introduced for small values of p, observing interesting figures, particularly for modular division. Whereas, polynomial arithmetic operations over GF(p) are discussed adequately in order to examine the potential for processes concurrency. In particular, polynomial division and multiplication are revisited in order to derive their iterative equations, which are suitable for systolic array implementation. Consequently, several designs are proposed for each individual process and their complexities are analyzed and compared. Subsequently, a concurrent divider/multiplier-accumulator is developed, while the resulting systolic architecture is utilized to build the EEA-based inverter.

Systolic design space exploration of EEA-based inversion over binary and ternary fields

A generalized version of the plus-minus algorithm is used for implementing dividers over GF(p/sup n/). Generic dividers have been synthesized in the general case of GF(p/sup n/) and in the particular cases of GF(2/sup n/) and GF(p). The theoretical costs are O(logN) being N the number of field elements, and the theoretical computation times are O(logN) in the case of dividers over GF(p/sup n/) and GF(2/sup n/), and O((logN)/sup 2/) in the case of dividers over GF(p). Finally, the results of FPGA implementations are reported, and a comparison is made between dividers over GF(p), GF(2/sup n/) and GF(p/sup n/).

Finite field division implementation

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Finite field division implementation