The use of in-line test struc(ures for routinely monitoring various high frequency aspects of the performance of CMOS gates is described. These compact test structures use dc I/O's and are compatible with standard parametric testers. The specific examples described are ring oscillators for a wide range of self-consistent parameter extraction ranging from circuit delays to gate length and leakage components; and a new class of self-timed calibrated structure of which a circuit for measuring SOI switching history effects utilizing loops time-scale, self- generated pulses is presented as a representative example.

High Speed Test Structures for In-Line Process Monitoring and Model Calibration

The use of in-line test structures for routinely monitoring various high frequency aspects of the performance of CMOS gates is described. These compact test structures use DC I/Os and are compatible with standard parametric testers. The specific examples described are ring oscillators for a wide range of self-consistent parameter extraction ranging from circuit delays to gate length and leakage components; and a new class of self-timed/calibrated structure of which a circuit for measuring SOI switching history effects, utilizing 100 ps time-scale self-generated pulses, is presented as a representative example.

High speed test structures for in-line process monitoring and model calibration [CMOS applications]

The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.

Challenges for future semiconductor manufacturing

Multiple Gate Field Effect Transistors (MuGFET) with a fin pitch down to 50nm obtained with 193nm optical lithography and proposed fin quadrupling patterning method are demonstrated. The fins patterned with this technique feature improved CD control and line width roughness. High fin density in combination with Si-SEG that allows merging individual fins outside the spacer region lead to reduction in parasitic source/drain-resistance and 3-fold increase in drive current per surface unit.

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

The role of single wafer Rapid Thermal Processing (RTP) in semiconductor manufacturing has been steadily expanding over the last 2 decades. There are several reasons for the successful adaptation of this technology. These include more critical requirements by advanced semiconductor technologies with respect to thermal exposure and control, as well as tremendous improvements by the RTP equipment community in resolving some fundamental limitations of the tooling, historically restricting wide spread implementation. From rather humble beginnings, RTP technology has now established itself as indispensable to the production of advanced semiconductor products. We review the history and implementation of RTP technology in semiconductor processing technology at International Business Machines Corporation (IBM) from the late 1980s to recent time.

The Expanding Role of Rapid Thermal Processing in CMOS Manufacturing

We present enhanced 90 nm node CMOS devices on a partially depleted SOI with 40 nm gate length, featuring advanced process modules for manufacture, including RSD (raised source/drain), disposable spacer, final spacer for S/D doping and silicide proximity, NiSi, and thermally optimized MOL (middle-of-line) process. For the first time, we systematically designed silicide proximity in SOI and post-activation thermal cycles to improve series resistance and gate activation. This paper demonstrates decoupled effects of the individual performance boosters on drive currents and minimization of dopant deactivation, which resulted in dramatic improvement of drive currents by 11% to 19% (820 /spl mu/A/um and 420 /spl mu/A/um at Ioff = 40 nA/um with Vdd = 1.0 V, for NFET and PFET, respectively), significant reduction in effective gate oxide thickness under gate inversion by /spl sim/1.2 /spl Aring/ and /spl sim/2.1 /spl Aring/, for NFET and PFET, respectively, and an excellent inverter delay of less than 5.4 ps at Lgate of 40 nm.

High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering

Body voltage (Vb) control in partially-depleted Silicon-on-Insulator (PD-SOI) is one of the critical technology parameters to achieve high performance devices. The floating body effect (FBE) introduces a history dependency in AC operation mode as well as an increase in drain-induced-barrier-lowering (DIBL) in DC mode. Gate oxide scaling significantly increases this history due to the exponential increase in gate oxide tunneling current on thickness reduction. In this paper, the sensitivity of key device parameters on the history effect is evaluated on a 90 nm device node. We demonstrate that the control of the diode current between body and source and drain is one of the most sensitive and promising techniques to reduce the history effect as well as increasing the DC device performance.

Body voltage and history effect sensitivity to key device parameters in 90 nm PD-SOI

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High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering

Body voltage and history effect sensitivity to key device parameters in 90 nm PD-SOI