Process variation has forever been the major fail cause of analog circuits where small deviations in component values cause large deviations in the measured output parameters. This paper presents a new approach for parametric fault simulation and test vector generation. The proposed approach utilizes the process information and the sensitivity of the circuit principal components in order to generate statistical models of the fault-free and the faulty circuit. The obtained information is then used as a measurement to quantify the testability of the circuit. This approach, extended by hard fault testing, has been implemented as automated tool set for IC testing called FaultMaxx and TestMaxx.

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Parametric fault simulation and test vector generation

This paper proposes a methodology, based on the regularization theory, to find the planar spiral inductors with optimum quality factor in the whole space of geometric parameters. Moreover a new technique, based on the Debye approximation, has been applied to extract an equivalent circuit model of these inductors. This model provides an accurate wideband frequency characterization up to 30 GHz.

Design and Modeling of Optimum Quality Spiral Inductors With Regularization and Debye Approximation

Lavrentiev: Some Improperly Posed Problems of Math. Physics/Watson u. Nuttall: Topics in Several Particle Dynamics/Heim: Schaltungsalgebra/Magnus, Karrass und Solitar: Combinatorial Group Theory/Migdal: Theory of Finite Fermi Systems and Applications to A

This paper presents a methodology, based on the regularization theory, to find, in the whole geometric parameter space, the planar spiral inductors with optimum quality factor. A new technique, based on Debye fitting approximation, has been applied to extract a passive equivalent circuit model of these inductors. This model provides an accurate wideband frequency characterization up to 16 GHz.

A Methodology for Design and Modeling of Optimum Quality Spiral Inductors

This paper presents a methodology, based on regularization theory, to find, in the whole geometric parameter space and for any value of mean inductance, the planar spiral inductor with optimum quality factor. The full-wave electromagnetic simulations of these inductors have been applied to the development of a parameterized circuit model. This model provides an accurate wide-band frequency characterization in the range from 1 GHz to 10 GHz.

Circuit Modelling of Optimum Quality Spiral Inductors based on Regularization Theory

Adequate analytical device models for circuit simulators are required in the design of IC's, especially in analog design, because the reliability of simulation results is closely related to model accuracy. A semiempirical approach to device modeling offers many advantages over physics-based modeling, in which complex equations have to be solved, and seems to be the most appropriate for circuit simulation. However as this approach is not founded on a rigorous mathematical theory no general methodologies are available for its implementation. Furthermore, device models currently used in circuit simulators are derived by neglecting randomness in experimental data. This assumption is not realistic for mass-produced IC's where technological tolerances cause variations in the measured data, even if they are obtained using the same experimental conditions. The aim of this work is to develop a new scheme for semiempirical device modeling founded on the rigorous mathematical framework of "regularization theory" and to suggest a parameter extraction method based on Bayesian parameter estimation, which takes into account randomness in data. The application of the method to the development of an accurate model for MOS transistors shows the validity of the proposed theoretical approach which is further confirmed by extensive analysis of experimental data.

Analytical device modeling for MOS analog IC's based on regularization and Bayesian estimation

This paper proposes an empirical MOSFET model, supported by statistically significant data derived from measurements on test-structures. The model, due to its accuracy, can be useful in predicting "a priori" fabrication process tolerances on ICs performances and in carrying out a combined "process-circuit" performances optimization.

An efficient method to predict drain current dispersion in MOS transistors from technological parameters fluctuations

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Analytical device modeling for MOS analog IC's based on regularization and Bayesian estimation

An efficient method to predict drain current dispersion in MOS transistors from technological parameters fluctuations