Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L/sub eff/), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L/sub eff/ on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.

Nanoscale FinFETs with gate-source/drain underlap

Since Moore’s law driven scaling of planar MOSFETs
faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing
to the presence of multiple (two/three) gates, FinFETs/Trigate
FETs are able to tackle short-channel effects (SCEs) better than
conventional planar MOSFETs at deeply scaled technology nodes
and thus enable continued transistor scaling. In this paper, we
review research on FinFETs from the bottommost device level
to the topmost architecture level. We survey different types of
FinFETs, various possible FinFET asymmetries and their impact,
and novel logic-level and architecture-level tradeoffs offered by
FinFETs. We also review analysis and optimization tools that
are available for characterizing FinFET devices, circuits, and
architectures.

/pdf/finfets-from-devices-to-architectures-3wvjf3zgcz.pdf

FinFETs: From Devices to Architectures

A self-consistent Poisson-Schro/spl uml/dinger solver is used to calculate the current in trigate n-channel silicon-on-insulator transistors with sections down to 2 nm /spl times/ 2 nm. The minimum energy of the subbands and the threshold voltage increase as the cross-sectional area of the device is reduced and as the electron concentration in the channel is increased. As a consequence, the threshold voltage is higher than predicted by classical Poisson solvers. The current drive is diminished, and the subthreshold slope is degraded, especially in the devices with the smallest cross sections.

Quantum-mechanical effects in trigate SOI MOSFETs

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

Perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated. The unique process used to fabricate these devices allow them to be integrated with FinFET devices. Device and circuit simulations have been used to explain the device and explore new applications using this device. A novel application of the MIGFET as a signal mixer has been demonstrated. The undoped channel, very thin body, perfectly matched gates allows charge coupling of the two signals and provide a new family of applications using the MIGFET mixer. Since the process allows integration of regular CMOS double gate devices and MIGFET devices this technology has potential for various digital and analog mixed-signal applications.

CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)

A process/physics-based compact model (UFDG) for nonclassical MOSFETs having ultra-thin Si bodies (UTB) is overviewed. The model, in essence, is a compact Poisson–Schrodinger solver, including accountings for short-channel effects, and is applicable to nanoscale fully depleted (FD) SOI MOSFETs as well as generic double-gate (DG) devices. The utility of UFDG in nonclassical CMOS device design, as well as circuit design, is stressed, and demonstrated by using it in Spice3 to design UTB MOSFETs and to project extremely scaled DG and FD/SOI CMOS performances. Also, calibration of UFDG to fabricated FinFETs yields new physical insights about these potentially viable nanoscale DG devices, and about model requirements for them.

A process/physics-based compact model for nonclassical CMOS device and circuit design

Physics-based compact modeling, as opposed to the conventional empirical approach, is emphasized for nanoscale nonclassical CMOS. UFDG, a physics-based compact model for generic double-gate MOSFETs with ultra-thin bodies, is overviewed, and its applications to double- and (multiple) independent-gate FinFET device and circuit design are demonstrated.

Physics-based compact modeling for nonclassical CMOS

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A process/physics-based compact model for nonclassical CMOS device and circuit design

Physics-based compact modeling for nonclassical CMOS