Studying dopant diffusion from Poly-Si passivating contacts

A process and apparatus for a high-k gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extend beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.

Method and apparatus for a semiconductor device with a high-k gate dielectric

The amount of atoms diffused into a substrate may be made uniform or the thickness of a thin film may be made uniform in a low species utilization process by stopping the flow of gas into a reaction chamber during the low species utilization process. Stopping the flow of gas into a reaction chamber may entail closing the gate valve (the valve to the vacuum pump), stabilizing the pressure within the reaction chamber, and maintaining the stabilized pressure while stopping the gas flowing into the chamber. Low species utilization processes include the diffusion of nitrogen into silicon dioxide gate dielectric layers by decoupled plasma nitridation (DPN), the deposition of a silicon dioxide film by rapid thermal processing (RTP) or chemical vapor deposition (CVD), and the deposition of silicon epitaxial layers by CVD.

Elimination of flow and pressure gradients in low utilization processes

A method for forming a dielectric is disclosed. The method comprises forming a first dielectric layer over semiconductor material. A diffusion barrier material is introduced into the first dielectric layer. Lastly, a second dielectric layer is formed over the first dielectric layer after the introducing.

Multi-layer dielectric containing diffusion barrier material

A semiconductor device and process including a high-k gate dielectric is described. A substrate is provided, and a high-k gate dielectric material, preferably amorphous HfSiON, is deposited over the substrate. In preferred embodiments, the high-k dielectric material includes nitrogen. In a preferred embodiment, a silicon nitride layer is deposited using jet vapor deposition (JVD) on the high-k dielectric material. When the JVD nitride layer is deposited according to preferred embodiments, the layer has a low density of charge traps, it maintains comparable carrier mobility and provides better EOT compared to oxide or oxynitride. A second nitrogen-containing layer formed between the high-k dielectric and the gate electrode acts as a diffusion barrier. It also reduces problems relating to oxygen vacancy formation in high-k dielectric and therefore minimizes Fermi-level pinning.

Semiconductor device and method for high-K gate dielectrics

Balancing gate leakage reduction, device performance, and gate dielectric reliability is a major challenge for oxynitride used as a gate dielectric for advanced technology. As compared to RTONO oxynitride, pMOSFET threshold voltage shift and transconductance degradation have been problematic for devices using remote plasma nitridation (RPN) or decoupled plasma nitridation (DPN) process due to non-optimal nitrogen profile in the film. In this paper, we report that the nitrogen profile of DPN gate dielectric can be engineered primarily by tuning the plasma pressure after optimizing other DPN process parameters to solve these problems. An EOT of 15 /spl Aring/ (23-/spl Aring/ NMOS CETinv) DPN oxynitride is demonstrated to have an acceptable pMOS Vt, comparable transconductance, significantly (/spl sim/30/spl times/) longer pMOS time-to-breakdown reliability for packaged devices, and 5/spl times/ gate leakage reduction relative to a high quality RTONO used in industry. The high quality ultrathin DPN film is fabricated in a commercially available system, which is compatible with standard CMOS processing technology. These encouraging results make high-pressure DPN oxynitride an attractive gate dielectric candidate for 80-nm advanced technology and beyond.

Ultra-thin decoupled plasma nitridation (DPN) oxynitride gate dielectric for 80-nm advanced technology

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Ultra-thin decoupled plasma nitridation (DPN) oxynitride gate dielectric for 80-nm advanced technology