A 60 GHz switched beam chip-to-chip antenna array is introduced. The array consists of four center fed circular patch elements with side vias in a $2{\times} 2$ grid arrangement forming a planar array. The array is designed to fit on a typical multicore chip for reconfigurable interchip wireless communication. The array main beam is switched by changing the interelement phase shifts in the azimuth plane. The switching of the main beam is analyzed and verified through full-wave simulation. The design presented is an improvement over a previous design of a two-element antenna array. The Friis transmission equation with polarization components taken into account is used to model the interchip wireless link. To verify the model, a transmission coefficient measurement is made between a pair of the two-element arrays separated by a 10 mm distance. Both simulated and measured radiation patterns of the two-element array are presented for use in the Friis equation to calculate the transmission coefficients. Full-wave simulation of the array pair is also performed. The calculated results obtained from the Friis model agree well with both the measured and full-wave simulation results. The Friis model is used to calculate both signal and interference levels.

Chip-to-Chip Switched Beam 60 GHz Circular Patch Planar Antenna Array and Pattern Considerations

This work describes the circuit and physical design implementation of the processor chip (CP), level-4 cache chip (SC), and the multi-chip module at the heart of the EC12 system. The chips were implemented in IBM's high-performance 32nm high-k/metal-gate SOI technology. The CP chip contains 6 super-scalar, out-of-order processor cores, running at 5.5 GHz, while the SC chip contains 192 MB of eDRAM cache. Six CP chips and two SC chips are mounted on a high-performance glass-ceramic substrate, which provides high-bandwidth, low-latency interconnections. Various aspects of the design are explored in detail, with most of the focus on the CP chip, including the circuit design implementation, clocking, thermal modeling, reliability, frequency tuning, and comparison to the previous design in 45nm technology.

Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module

A two-dimensional Butler matrix feed network is designed, implemented, and integrated with a 60 GHz 2 × 2 circular patch planar array for chip-to-chip communications. The realized antenna module is a thin multilayer microstrip structure with a footprint small enough to fit over a typical multicore chip. The network enables endfire (azimuthal) scan of the array main beam in the four diagonal directions, which is demonstrated for the first time in this letter. The antenna module provides a seamless and practical way to achieve reconfigurable interchip communication in multicore multichip (MCMC) systems. A hybrid space-surface wave interconnect is proposed that takes advantage of surface-wave coupling. The matrix is a four-input, four-output, i.e., 4 × 4, network consisting of four interconnected quadrature (90 $^\circ$ ) hybrid couplers. A multiantenna module (MAM) consisting of five antenna modules that emulates diagonal interchip communication in MCMC systems is fabricated. The simulation and measurement of transmission coefficients between the antenna modules on the MAM are performed and compared.

/pdf/switched-beam-endfire-planar-array-with-integrated-2-d-4b94ohqyng.pdf

Switched-Beam Endfire Planar Array With Integrated 2-D Butler Matrix for 60 GHz Chip-to-Chip Space-Surface Wave Communications

AI acceleration is one of the most actively researched fields in IP and system design. The introduction of specialized AI accelerators in the cloud and at the edge has made it possible to deploy large scaled AI solutions that automate tasks that were previously not possible without AI. The growth of big data and the compute horsepower needed to process this data to provide business intelligence is key for several companies in gaining a competitive edge. AI workloads are both data and compute intensive and improving the efficiency often requires an end-to-end solution. In this perspective paper, we identify key considerations for the design of AI accelerators. The focus of this paper is on Deep Neural Networks (DNN) and how to build efficient deep neural network accelerators through microarchitectural exploration, energy efficient memory hierarchies, flexible dataflow distribution, domain-specific compute optimizations and finally hardware-software co-design techniques. The importance of interconnect topology and the impact of its scaling to the physical design of an AI accelerator is also a key consideration that is described in this paper. In the future, the energy efficiency of these accelerators may rely on approximation computing, compute-in-memory and runtime flexibility for significant improvement.

Design Considerations for Edge Neural Network Accelerators: An Industry Perspective

The IBM z14 is the latest update in the storied history of IBM mainframes. Reliability, availability, security, and scalability are the foundation of the IBM mainframe line. System reliability and availability targets are in excess of 10 years, requiring rigorous chip characterization processes. In this paper, we discuss some of the many processes used to ensure that lifetime. An additional part of this reliability is power management (PM). The 5.2-GHz high-power design of the central processor chip requires advanced on-die PM capabilities to adapt to power intensive instruction streams. We also discuss a number of improvements to the critical path monitoring design used to manage power supply voltage droops, reducing response time and the impact on system performance. Finally, we compare a set of simulations and hardware results to validate our power fluctuation models.

IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems

This paper describes the circuit and physical design features of the z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order processor cores, running at 5.2 GHz, on a die with an area of 512 mm2 containing an estimated 1.4 billion transistors. The core and chip design methodology and specific design features are presented, focusing on techniques used to enable high-frequency operation. In addition, chip power, IR drop, and supply noise are discussed, being key design focus areas. The chip's ground-breaking RAS features are also described, engineered for maximum reliability and system stability.

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

G. Gerwig

Author Tools

Chat about Author

Papers

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System