This paper presents the design and study of an architecture able to perform 10 Gbit/s GFP frame delineation with single bit error correction on an FPGA. The design targets the development of a system-on-chip (SoC) platform for the design of next generation network processing. In order to achieve the high processing rate, the circuit is designed with a 64-bit data-path and is targeted to Altera Stratix II FPGA technology. The circuit operates at a clock rate of 165 MHz. The circuit utilises 8 parallel CRC HEC calculators and comparators, a PLI frame counter and a single bit error correction mechanism.

A 10 Gbps GFP frame delineation circuit with single bit error correction on an FPGA

This paper presents the design and study of circuit architectures for gigabit GFP frame delineation and explores the trade-offs between the data-path (parallelism) and the corresponding hardware cost. The study targets the development of a SoC platform for the design of next generation network processing. Circuits with an 8-bit, 16-bit, 32-bit and a 64-bit data-path have been implemented and analysed in terms of, scalability, hardware cost, speed, and data throughput capabilities. The circuit analysis is based on performance results with the UMC 0.18 /spl mu/m standard cell libraries obtained using Synopsys physical compiler. Analysis shows that the 64-bit datapath architecture is able to achieve data rates beyond l0Gbps whereas the 8-bit data-path architecture is very compact and operates with a clock rate of close to 300MHz. Considering the throughput-rate versus silicon area cost as a measure of silicon area efficiency, then the 16-bit data-path architecture proves to be the most efficient.

Exploration of GFP frame delineation architectures for network processing

This paper presents the design and study of various HEC hunt architectures for ATM frame delineation and explores the trade-offs between the data-path (parallelism) and the hardware cost. A bit-serial, 4-bit, 8-bit, 32-bit and a 64-bit HEC hunt circuit has been implemented and analysed in terms of hardware cost, speed, and data throughput rate. The performances of the bit-parallel architectures have been improved by further pipelining the computation circuit. In the case of the 64-bit data-path architecture, the data throughput capability increased by 63% with an area penalty of only 20%. Post layout results are presented for Altera Stratix FPGA technology.

The Implementation of Scalable ATM Frame Delineation Circuits

This study presents a novel bridge chip between an asynchronous transfer mode (ATM) and Ethernet for an asymmetric digital subscriber line (ADSL) in home network which fabricated in a standard 0.18-mum 1P6M CMOS process. The proposed bridge chip is an ASIC designed with hardware description language (HDL) and fabricated using a cell-based digital IC design flow. The proposed chip merges two independent chips; transmitter-end and receiver-end chips, into a single chip, and eliminate the RISC processor to reduce production cost. Moreover, system stability and transmission capacity are enhanced due to the small chip area. Chip specifications are a power supply of 1.8 V and system operating frequency of 50 MHz.

A novel bridge chip between an ATM and ethernet for ADSL in home networks

/pdf/investigation-into-programmability-for-layer-2-protocol-36gwsbpnbc.pdf

Investigation into programmability for layer 2 protocol frame delineation architectures

Several algorithms for performing cell delineation on a bit-serial and octet-parallel basis are considered. Four algorithms were implemented in total, two bit-serial and two octet-parallel, for the design of cell delineators through to netlist generation. Analysis is provided for post-synthesis designs detailing speed, area and power parameters for each implementation at an input data rate of 160 Mbps and 1280 Mbps.

Asynchronous transfer mode cell delineator implementations

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Asynchronous transfer mode cell delineator implementations