This paper presents design and mathematical noise model of front-end electronics for a silicon particle detector , considering the complete transfer function of a charge sensitive amplifier (CSA). The work includes the noise and crosstalk analysis of a pixel array with a conventional CSA and a zero-pole transformation CSA (ZPT–CSA) (Jaffari et al., 2011). The pixel array has been designed and simulated in a 180 nm CMOS technology with the supply voltage of 1.8 V and the substrate potential of –10 V. The comparative study for conventional and ZPT–CSA is performed with the circuit simulations. The study demonstrates a reduction of 30 % in output noise spectral density and 46 % in equivalent noise charge (ENC) for a frequency band of 100 kHz–100 MHz by using a zero-pole transformation technique. Further, the paper proposes systematic design criteria for a ZPT–CSA with a continuous reset mechanism for the noise reduction. The complete transfer function for the ZPT–CSA is derived and noise model is presented in the presence of interpixel capacitive crosstalk. The results of the mathematical model are compared with the circuit simulations. An average error of 3 × 1 0 − 10 V 2 ∕ Hz is seen in the output noise voltage spectral density for a frequency range of 100 kHz to 100 MHz. The comparison shows an average relative error of 1.8% for the crosstalk voltages. ENC from both the simulations has an average error of 2.91 aC ( ∼ 18 electrons) when plotted for a pixel capacitance range of 10 fF–100 fF in 100 kHz to 100 MHz frequency band.

Noise and crosstalk models of the particle detector with zero-pole transformation charge sensitive amplifier

The paper presents design and implementation of a silicon particle detector array with the derived closed form equations of signal-to-noise ratio (SNR) and crosstalk voltages. The noise analysis demonstrates the effect of interpixel capacitances (IPC) between center pixel (where particle hits) and its neighbouring pixels, resulting as a capacitive crosstalk. The pixel array has been designed and simulated in a 180 nm BCD technology of STMicroelectronics. The technology uses the supply voltage (VDD) of 1.8 V and the substrate potential of −50 V. The area of unit pixel is 250×50 μm2 with the substrate resistivity of 125 Ωcm and the depletion depth of 30 μm. The mathematical model includes the effects of various types of noise viz. the shot noise, flicker noise, thermal noise and the capacitive crosstalk. This work compares the results of noise and crosstalk analysis from the proposed mathematical model with the circuit simulation results for a given simulation environment. The results show excellent agreement with the circuit simulations and the mathematical model. The average relative error (AVR) generated for the noise spectral densities with respect to the simulations and the model is 12% whereas the comparison gives the errors of 3% and 11.5% for the crosstalk voltages and the SNR results respectively.

https://iopscience.iop.org/article/10.1088/1748-0221/13/01/C01019/pdf

Analytical expressions for noise and crosstalk voltages of the High Energy Silicon Particle Detector

Monochromatic X and gamma rays are a standard calibration tool for semiconductor detector. For finely segmented pixel detectors, like the ones foreseen for HL-LHC detector upgrades, the single pixel spectrum is affected by charge sharing across nearby pixels, due to diffusion and the finite range of photoelectrons , resulting in a low energy continuum below the photoelectric peak. In this paper a systematic simulation study will be presented. The shape of the transition between the photoelectric peak and the continuum is determined by diffusion and needs to be unfolded for a correct estimation of the energy resolution. Simulation results are compared with data collected with different high-resistivity CMOS devices with 50 × 250 μ m2 pixel size and photon energies between 13 and 60 keV. They show a good agreement, highlighting the potential usage of the whole single pixel spectrum to derive device characteristics.

Charge sharing of single photons in finely segmented pixel detectors

This paper presents the design and implementation of a particle detector in a Bipolar-CMOS-DMOS (BCD) 180 nm technology. The design has a substrate potential of — 50 V and supply voltage of 1.8 V. Size of the unit pixel sensor is $250\times 50\ \mu\mathbf{m}^{2}$ . The chip consists of an array of $47\times 6$ pixels including the signal processing circuitry. The total chip area is $3.3 \times 4.4\ \mathbf{mm}^{2}$ . The complete signal processing circuitry is hosted inside the diode sensor to achieve 100% fill factor. The chip consists of 106 input-output pads, including the pads for supplies viz. — 50 V, 0 V and 1.8 V. The measurement results are presented to validate the noise and crosstalk models of the designed detector. The comparison shows an average mismatch of 2.65 $\mu\mathbf{V}$ for the crosstalk voltages in a range of 3000 to 7000 injected electrons. The circuit noise has an average mismatch of $1.23\times 10^{-10}\ \mathbf{V}^{2}/\mathbf{Hz}$ between the analytical and the measurement results for a frequency range of 100 kHz to 22 MHz. The analog processing circuitry provides a measured voltage gain of 33.3 dB at 100 kHz of input frequency.

Design of HV-CMOS Detectors in BCD Technology with Noise and Crosstalk Measurements

The paper presents the research activities in microelectronics, aiming at improving detection capabilities of future High Energy Physics (HEP) experiments. The output of this research will be the development of novel integrated circuits, to enhance the performance of electronic systems for the High Luminosity Large Hadron Collider (HL-LHC). In particular, the main research activities are focused on monolithic pixel arrays, on new digital architectures for pixel readout in 65 nm CMOS, and on associative memories for several interdisciplinary applications, such as fast tracking for trigger, DNA sequencing, magnetic resonance and image analysis.

R&D on Electronic Devices and Circuits for the HL-LHC

This paper presents the first pixel detector realized using the BCD8 technology of STMicroelectronics. The BCD8 is a 160 nm process with bipolar, CMOS and DMOS devices; mainly targeted for an automotive application. The silicon particle detector is realized as a pixel sensor diode with a dimension of 250 × 50 μm2. To support the signal sensitivity of pixel diode, the circuit simulations have been performed with a substrate voltage of 50 V. The analog signal processing circuitry and the digital operation of the circuit is designed with the supply voltage of 1.8 V. Moreover, an analog processing part of the pixel detector circuit is confined in a unit pixel (diode sensor) to achieve 100 % fill factor. As a first phase of the design, an array of 8 pixels and 4 passive diodes have been designed and measured experimentally. The entire analog circuitry including passive diodes is implemented in a single chip. This chip has been tested experimentally with 70 V voltage capability, to evaluate its suitability. The sensor on a 125 Ωcm resistivity substrate has been characterized in the laboratory. The CMOS sensor realizes a depleted region of several tens of micrometer. The characterization shows a uniform breakdown at 70 V before irradiation and an approximate capacitance of 80 fF at 50 V of reverse bias voltage. The response to ionizing radiation is tested using radioactive sources and an X-ray tube.

HV-CMOS detectors in BCD8 technology

Radiation detectors built in high-voltage and high-resistivity CMOS technology are an interesting option for the large area pixel trackers sought for the upgrade of the Large Hadron Collider experiments. A possible architecture is a hybrid design, where CMOS sensors are readout by front-end electronics coupled through a thin dielectric layer. A critical requirement is the radiation hardness of both the sensor and the front-end circuitry, up to a total dose ranging from 100 Mrad to 1 Grad (1 MGy to 10 MGy), depending on the distance from the interaction region. This paper explores the suitability of the BCD8 technology provided by STMicroelectronics for the construction of radiation-hard pixel detectors together with a technique to achieve reliability and repeatability of the hybridization process between the detector and the readout chip.

HV-CMOS detectors for high energy physics: Characterization of BCD8 technology and controlled hybridization technique

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HV-CMOS detectors in BCD8 technology

HV-CMOS detectors for high energy physics: Characterization of BCD8 technology and controlled hybridization technique