A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Method for fabrication of a semiconductor device and structure

A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Controlled cleaving process

Methods for manufacturing semiconductor substrates in which a semiconductor layer for forming semiconductor device therein is formed on a supporting substrate with an insulating film interposed between, with which in forming the semiconductor layer on a substrate on which a buried pattern structure has been formed it is possible to greatly increase the film thickness uniformity of the semiconductor layer and the film thickness controllability, particularly when the semiconductor layer is being formed as an extremely thin film. As a result, it is possible to achieve improved quality and characteristics of the semiconductor substrates and make possible the deployment of such semiconductor substrates to various uses.

Method for manufacturing a semiconductor substrate

Silicon-on-Insulator devices having a buried capacitor structure have been proposed by several authors as a 1 giga bit DRAM cell structure. However, several limits such as wafer cost, low throughput, and poor SOI thickness uniformity would prevent the practical application of this technology in spite of its distinct advantages such as shorter process step, easier backend process, and higher packing density. In this paper, we demonstrated the feasibility of a novel pattern transfer method combining the hydrogen implantation and selective polish stop process which can be applied to the fabrication of buried capacitor SOI structure with a low cost and high throughput.

http://ieeexplore.ieee.org/iel3/4073/11984/00552520.pdf

A novel pattern transfer process for bonded SOI giga-bit DRAMs

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A novel pattern transfer process for bonded SOI giga-bit DRAMs