A new mobility degradation specific to short channel MOSFETs is studied and elucidated. Pocket implants/dopants pile-up, interface states/oxide charges, remote Coulomb scattering or ballisticity are insufficient to explain this degradation. The role of non-Coulombian (neutral) defects, which can be healed by increasing the annealing temperature, is evidenced.

Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling

Preface List of physical constants List of symbols 1. Introduction 2. Unique features of UTB MOSFETs 3. Planar fully depleted SOI MOSFETs 4. FinFETs Appendix: UFDG References Index.

/pdf/fundamentals-of-ultra-thin-body-mosfets-and-finfets-2ldlpxa1to.pdf

Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs

A novel two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications is proposed and demonstrated via device/circuit simulations using a process/physics-based compact model, with numerical-simulation support. Significant advantages of the 2T cell, in which the charged/discharged body of one transistor (1T) drives the gate of the other, over the currently popular 1T-DRAM FBC are noted and explained. Furthermore, a modification of the basic 2T-FBC structure, which in essence results in a floating-body/gate cell (FBGC), is shown to yield dramatic reduction in power dissipation in addition to better signal margin, longer data retention, and higher memory density. Design and processing issues that need to be addressed for optimal performance and for sustained FBGC viability in nanoscale CMOS are discussed.

A Novel Two-Transistor Floating-Body/Gate Cell for Low-Power Nanoscale Embedded DRAM

A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel being substantially parallel to the first channel within a first plane, wherein the first plane is parallel to a major surface of a substrate over which the first channel lies. A gate electrode is formed surrounding the first channel and the second channel in a second plane, wherein the second plane is perpendicular to the major surface of the substrate. The resulting semiconductor device has a plurality of locations with a plurality of channels at each location. At small dimensions the channels form quantum wires connecting the source and drain.

Multi-channel transistor structure and method of making thereof

A novel nanoscale hybrid device (the ITFET) comprising a double-gate (DG) FinFET and a single-gate silicon-on-insulator (SOI) MOSFET, with a common gate, is defined and assessed using a process/physics-based compact model [University of Florida DG model (UFDG)] and 3-D numerical simulations. Significantly higher, and variable, on-state current per pitch, relative to the current of the FinFET, can be achieved with a properly designed ITFET, with the off-state current being governed by the body thickness of the (fully depleted) SOI device. The ITFET can be especially advantageous in FinFET circuits that require device ratioing, such as the 6T-static random access memory (SRAM) cell. Outstanding UFDG/Spice3-predicted characteristics of the FinFET-based SRAM cell, with ITFETs used for the pull-down transistors without any area penalty, are presented

The ITFET: A Novel FinFET-Based Hybrid Device

In this paper we demonstrate for the first time a novel CMOS IT-FET (inverted T channel FET) architecture. We demonstrate well functional ITFET SRAM bit-cells. Vertical devices such as FinFET and planar ultra thin body devices have been shown to exhibit good short channel control and proposed for future device scaling. The ITFET is novel device architecture that takes advantage of both vertical and horizontal thin-body devices. A doped channel IT-FET process has been developed and is the focus of this paper. This technology can be scaled beyond 45nm technologies using undoped channels. An ITFET device comprises of an ultra thin body planar horizontal channels and vertical channels in a single device. The devices have multi-gate control around these channels to improve short channel control. A single device has multiple orientations and hence mobility enhancement of both (110) and (100) planes can be used optimally. The devices presented have 15nm planar horizontal thin body and 40nm vertical channels of 100nm height, 17Aring gate dielectric and 50nm gate length. These devices are especially useful in circuits that need ratioing such as in SRAM cells and a well functional SRAM cell is demonstrated

Inverted T channel FET (ITFET) - Fabrication and characteristics of vertical-horizontal, thin body, multi-gate, multi-orientation devices, ITFET SRAM bit-cell operation. A novel technology for 45nm and beyond CMOS.

The ITFET is novel device architecture; it offers significant advantages over planar and FinFET technologies. The ITFET uses traditional CMOS processing technologies and can be rapidly inserted into existing SOI process flows. Doped channel ITFET devices have been demonstrated future work will include undoped channel ITFET devices. Simulated performances of the ITFET devices predict these devices can meet the 45nm and 32nm device performance. This transistor architecture offers device, process and application advantages

ITFET: Inverted T Channel FET, A Novel Device architecture and circuits based on the ITFET

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Inverted T channel FET (ITFET) - Fabrication and characteristics of vertical-horizontal, thin body, multi-gate, multi-orientation devices, ITFET SRAM bit-cell operation. A novel technology for 45nm and beyond CMOS.

ITFET: Inverted T Channel FET, A Novel Device architecture and circuits based on the ITFET