Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults.Additionally, Virtual Prototypes (VPs) have been accepted in many areas of system development processes in the automotive industry as platforms for SW development, verification, and design space exploration. We believe that VPs will significantly contribute to the analysis of safety conditions for automotive electronics. This paper shows the advantages of such a methodology based on today's industrial needs, presents the current state of the art in this field, and outlines upcoming research challenges that need to be addressed to make this vision a reality.

Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges

This paper presents the XEMU framework for mutation based testing of embedded software binaries. We apply an extension of the QEMU software emulator, which injects mutations at run-time by dynamic code translation without affecting the binary software under test. The injection is based on a mutation table, which is generated by control flow graph (CFG) analysis of the disassembled code prior to its execution without presuming access to source code. We introduce our approach by the example of the ARM instruction set architecture for which a mutation taxonomy is presented. In addition to extending the testing scope to target specific low level faults, XEMU addresses the reduction of the mutants creation, execution, and detection overheads. Moreover, we reduce testing efforts by applying binary CFG analysis and constraint-based test generation for improved test quality. The experimental results of a car motor management software show significant improvements over conventional source code based approaches while providing 100% accuracy in terms of the computed test quality metrics.

XEMU: an efficient QEMU based binary mutation testing framework for embedded software

At present, the functional verification of a device represents the highest cost during manufacturing. To reduce that cost, several methods have been suggested. In this work we propose a method which produces a set of binary test sequences by means of a Compact binary Differential Evolution algorithm (Compact-BinDE). The strategy employed is based on the use of coverage models and cost functions in the verification process, which are built with relevant conditions or coverage points representing the full device behavior. The main problem is to cover all difficult situations since the relationships between the test points and the input data in the design are not trivial. The test generation method is included with a proposed verification platform based on a simulation representing a hybrid method. The main contribution of this work is that the method obtains test vector sequences that maximize the coverage percentage on run-time device simulation with an efficient search in the binary domain. Also, different to the previous works that used meta-heuristics, the proposed method by means of the Compact-BinDE algorithm can reduce the simulation time used to obtain test sequences that exercise the coverage points. The results show that the proposed method represents a good alternative to generate test sequences to cover the coverage points during the functional verification.

Automated Functional Test Generation for Digital Systems Through a Compact Binary Differential Evolution Algorithm

This paper presents a novel mutation based testing method through binary mutation. For this, a table of mutants is derived by control flow analysis of a disassembled binary under test. Mutations are injected at runtime by dynamic translation. Thus, our approach neither relies on source code nor a certain compiler. As instrumentation is avoided, testing results correspond to the original binary. In addition to high-level language faults, the proposed approach captures target specific faults related to compiling and linking. We investigated the software of an automotive case study. For this, a taxonomy of mutation operators for the ARM instruction set is proposed. Our experimental results prove 100% accuracy w.r.t. confidence metrics provided by conventional testing methods while avoiding significant mutant compilation overhead. Further speed up is achieved by an efficient binary mutation testing framework that relies on extending the open source software emulator QEMU.

http://adt.cs.upb.de/wolfgang/dsn2012.pdf

Binary mutation testing through dynamic translation

The growing complexity and higher time-to-market pressure make the functional verification of modern large scale hardware systems more challenging. These challenges bring the requirement of a high quality testbench that is capable of thoroughly verifying the design. To reveal a bug, the testbench needs to activate it by stimulus, propagate the erroneous behaviors to some checked points, and detect it at these checked points by checkers. However, current dominant verification approaches focus only on the activation aspect using a coverage model which is not qualified and ignore the propagation and detection aspects. Using a new metric, this paper qualifies the testbench by mutation analysis technique with the consideration of the quality of the stimulus, the coverage model, and the checkers. Then the testbench is iteratively refined according to the qualification feedback. We have conducted experiments on two designs of different scales to demonstrate the effectiveness of the proposed method in improving the quality of the testbench.

/pdf/functional-testbench-qualification-by-mutation-analysis-1wzbp0gxkl.pdf

Functional testbench qualification by mutation analysis

HDL-mutation based fault injection and analysis is considered as an important coverage metric for measuring the quality of design simulation processes [20, 3, 1, 2]. In this work, we try to solve the problem of automatic simulation data generation targeting HDL mutation faults. We follow a search based approach and eliminate the need for symbolic execution and mathematical constraint solving from existing work. An objective cost function is defined on the test input space and serves the guidance of search for fault-detecting test data. This is done by first mapping the simulation traces under a test onto a control and data flow graph structure which is extracted from the design. Then the progress of fault detection can be measured quantitatively on this graph to be the cost value. By minimizing this cost we approach the target test data. The effectiveness of the cost function is investigated under an example neighborhood search scheme. Case study with a floating point arithmetic IP design has shown that the cost function is able to guide effectively the search procedure towards a fault-detecting test. The cost calculation time as the search overhead was also observed to be minor compared to the actual design simulation time.

http://adt.cs.upb.de/wolfgang/dsd2011.pdf

HDL-Mutation Based Simulation Data Generation by Propagation Guided Search

This paper proposes a quality driven, simulation based approach to functional design verification, which applies mainly to IP-level HDL designs with well specified test instruction format and is evaluated on a soft microprocessor core MB-LITE [5]. The approach utilizes mutation analysis as the quality metric to steer an automated simulation data generation process. It leads to a simulation flow with two phases towards an enhanced mutation analysis result. First in a random simulation phase, an in-loop heuristics is deployed and adjusts dynamically the test probability distribution so as to improve the coverage efficiency. Next, for each remaining hard-to-kill mutant, a search heuristics on test input space is developed to iteratively locate a target test, using a specific objective cost function for the goal of killing HDL mutant. The effectiveness of this integrated two-phase simulation flow is demonstrated by the results with the MB-LITE microprocessor IP.

http://adt.cs.upb.de/wolfgang/socc2012.pdf

Mutation-analysis driven functional verification of a soft microprocessor

Mutation-testing has been considered as an important coverage metric to measure the quality of simulation-based verification and validation processes [1, 2, 3]. On the other hand, IP-XACT has evolved to the IEEE standard for IP reuse and IP-based System-on-Chip (SoC) integration, which covers both RTL and TLM. In this paper, we present our effort to enable the mutation-based simulation coverage metric for system level IP integration with IP-XACT. Two major ingredients are required for this extension. First, as IP-XACT system designs are XML files, which are not originally for execution, we need an execution/simulation engine for IP-XACT designs. For this, we created a code generator that generates SystemC models from IP-XACT XML designs, such that we can simulate and test an IP-XACT design. Second, we define the mutation operators on IP-XACT schema, which is the model of errors that we can inject into IP-XACT designs during mutation testing. With IP-XACT, the mutation maintains a focus on the integration and configuration of components. We implemented the code generator and mutation operators in an Eclipsed-based IP-XACT editor with the help of Eclipse Modeling Framework. Then several experiments were conducted on a TLM library for CoreConnect SoC modeling. From the results, we can see that the defined IP-XACT mutation serves an effective qualification for simulation tests, in terms of its ability to reveal the weakness of the tests.

http://adt.cs.upb.de/wolfgang/hldvt2011.pdf

IP-XACT based system level mutation testing

Constrained random simulation based verification (CRV) becomes an important means of verifying the functional correctness of the increasingly complex hardware designs. Effective coverage metric still lacks for assessing the adequacy of these processes. In contrast to other coverage metrics, the syntax-based Mutation Analysis (MA) defines a systematic correlation between the coverage results and the test’s ability to reveal design errors. However, it always suffers from extremely high computation cost. In this paper we present an efficient integration of mutation analysis into CRV flows, not only as a coverage gauge for simulation adequacy but also, a step further, to direct a dynamic adjustment of the test probability distribution. We consider the distinct cost model of this MA-based random simulation flow and try to optimize the coverage process. From the probabilistic analysis of the simulation cost, a heuristics for steering the test generation is derived. The automated flow is implemented by the SystemC Verification Library and by CertitudeTM for mutation analysis. Results from the experiment with an IEEE floating point arithmetic design show the efficiency of our approach.

/pdf/efficient-mutation-analysis-coverage-for-constrained-random-2yvneqs78h.pdf

Efficient Mutation-Analysis Coverage for Constrained Random Verification

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HDL-Mutation Based Simulation Data Generation by Propagation Guided Search

Mutation-analysis driven functional verification of a soft microprocessor

IP-XACT based system level mutation testing

Efficient Mutation-Analysis Coverage for Constrained Random Verification