Advanced packaging technology has become more and more important in the semiconductor industry because of the benefits of higher I/O density compared to conventional soldering technology. In advanced packaging technology, copper-copper (Cu-Cu) bonding has become the preferred choice due to its excellent electrical and thermal properties. However, one of the major challenges of Cu-Cu bonding is the high thermal budget of the bonding process caused by Cu oxidation, which can result in wafer warpage and other back-end-of-line process issues in some cases. Thus, for specific applications, reducing the thermal budget and preventing Cu oxidation are important considerations in low-temperature hybrid bonding processes. This paper first reviews the advancements in low-temperature Cu-based bonding technologies for advanced packaging. Various low-temperature Cu-Cu bonding techniques such as surface pretreatment, surface activation, structure modification, and orientation control have been proposed and investigated. To overcome coplanarity issues of Cu pillars and insufficient gaps for filling, low-temperature Cu-Cu bonding used, but it is still challenging in fine-pitch applications. Therefore, low-temperature Cu/SiO2, Cu/SiCN, and Cu/polymer hybrid bonding have been developed for advanced packaging applications. Furthermore, we present a novel hybrid bonding scheme for metal/polymer interfaces that achieves good flatness and an excellent bonding interface without the need for the chemical mechanical polishing (CMP) process.

Cu-Based Thermocompression Bonding and Cu/Dielectric Hybrid Bonding for Three-Dimensional Integrated Circuits (3D ICs) Application.

Hybrid bonding is a major enabler for devices requiring 3D stacking with high interconnection density. An in-depth reliability study is performed for the specific Cu/SiO2 integration to identify the potential failure mechanisms. A high robustness is evidenced down to bonding pitch 0.81 μm for the standard reliability tests such as Thermal Cycling (TC) tests, High Temperature Storage (HTS) test, Stress induced Voiding (SiV), Time Dependent Dielectric Breakdown (TDDB) or electromigration. The hybrid bonding interface is stable under thermal stress with no atomic or ionic Cu diffusion observed through the hybrid bonding interface. The role of the thin self-formed cuprous oxide at the Cu/SiO2 interface in the case of misaligned bonding pads is believed to play a major role in the high robustness to reliability tests. 

Reliability of the hybrid bonding level using submicrometric bonding pads

This study presents groundbreaking outcomes of 400nm pitch wafer-to-wafer (W2W) hybrid bonding connections with a Cu/SiCN bonding interface. A new test vehicle is introduced and meticulously designed for the relevant process development and studies. To ensure a precise surface topography control after CMP, a hexagonal pad grid is adopted, with dummy pads strategically placed in the unused layout areas. The design contains a large range of pad pitches from 1000nm to 400nm, accommodating both equal and unequal pad size configurations. Improved underlayer topography control emerges as a significant factor in achieving void-free bonding. Furthermore, the measured electrical data demonstrates close alignment with simulated models, encompassing resistance and capacitance. The impact of local pad-to-pad overlay error on the electrical properties of hybrid bond pads are also explored in this paper. The findings confirm the necessity for a maximum vector overlay tolerance of 100nm for 400nm pitch connections. 

Scaling Cu/SiCN Wafer-to-Wafer Hybrid Bonding down to 400 nm interconnect pitch

Wafer-to-wafer (W2W) hybrid bonding has gained more attention as the Artificial intelligence (AI) and big data machine learning (ML) applications required higher interconnect densities. This paper presents our research to demonstrated Cu/SiCN W2W hybrid bonding down to PAD Pitch 700nm. We have proven good Cu-Cu connectivity performance in both long daisy chains and kelvin resistor devices. Atomic Force Microscope (AFM) measurement is used to analyze the pre-bonding materials properties, namely Cu PAD height, dielectric surface profile and roughness. This enables, together with good W2W hybrid bonding overlay control, high electrical yield.

700nm pitch Cu/SiCN wafer-to-wafer hybrid bonding

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700nm pitch Cu/SiCN wafer-to-wafer hybrid bonding