We propose Qubit4Sync, a synchronization method for Quantum Key Distribution (QKD) setups, based on the same qubits exchanged during the protocol and without requiring additional hardware other than the one necessary to prepare and measure the quantum states. Our approach introduces a new cross-correlation algorithm achieving the lowest computational complexity, to our knowledge, for high channel losses. We tested the robustness of our scheme in a real QKD implementation.

Fast and simple qubit-based synchronization for quantum key distribution

This brief proposes an efficient radix-2 single-path delay commutator (SDC) pipelined architecture to implement the fast Walsh–Hadamard–Fourier transform (FWFT) algorithm. The proposed architecture includes $(\log_{2}N-1)$ SDC stages, which are implemented by merged half-butterfly. The merged half-butterfly is proposed to achieve 100% hardware utilization and minimum buffer usage by sharing common merged half-butterflies in the time-multiplexed approach. Compared with the conventional pipelined radix-2 FFT+Walsh–Hadamard Transform (WHT) designs, the proposed architecture reduces the number of buffers by 50% and of adders by 25%. The required number of complex multipliers is decreased to $0.5\log_{2}N-0.5$ , which is roughly the minimum number. Moreover, the proposed architecture can be applied to FFT/WHT/sequence-ordered complex Hadamard transform (SCHT).

Pipelined Architecture for a Radix-2 Fast Walsh–Hadamard–Fourier Transform Algorithm

We propose Qubit4Sync, a synchronization method for quantum-key-distribution (QKD) setups, based on the same qubits exchanged during the protocol and without requiring additional hardware other than that necessary to prepare and measure the quantum states, in a similar fashion to the clock recovery used in classical communications. Our approach introduces a cross-correlation algorithm with low computational complexity for high channel losses. We test the robustness of our scheme in a real QKD implementation, and we believe it may find application in other quantum communication protocols.

Fast and Simple Qubit-Based Synchronization for Quantum Key Distribution

We present a hybrid pipelined sorting architecture capable of finding and producing as its output the $K$ largest elements from an input sequence. The architecture consists of a bitonic sorter and $L$ cascaded sorting units. The sorting unit is designed to output $P$ elements during every cycle with the aim of increasing the throughput and lowering the latency. The function of the bitonic sorter is to generate a segmented ordered sequence. The sorting unit processes this sequence to identify and output the $P$ largest elements. Hence, the $K = PL$ largest elements are obtained after the segmented ordered sequence proceeds through $L$ cascaded sorting units. Variable-length and continuous sequences are supported by the proposed sorting architecture. The results of the implementation show that the sorting architecture can achieve a throughput of 22.88 GB/s with $P = 16$ on a state-of-the-art Field Programmable Gate Array (FPGA).

A Hybrid Pipelined Architecture for High Performance Top- K Sorting on FPGA

We study the following basic pattern matching problem. Consider a "code" sequence c consisting of n bits chosen uniformly at random, and a "signal" sequence x obtained by shifting c (modulo n) and adding noise. The goal is to efficiently recover the shift with high probability. The problem models tasks of interest in several applications, including GPS synchronization and motion estimation.We present an algorithm that solves the problem in time O(n(f/(1+f)), where O(Nf) is the running time of the best algorithm for finding the closest pair among N "random" sequences of length O(log N). A trivial bound of f = 2 leads to a simple algorithm with a running time of O(n2/3). The asymptotic running time can be further improved by plugging in recent more efficient algorithms for the closest pair problem.Our results also yield a sub-linear time algorithm for approximate pattern matching algorithm for a random signal (text), even for the case when the error between the signal and the code (pattern) is asymptotically as large as the code size. This is the first sublinear time algorithm for such error rates.

Shift Finding in Sub-linear Time

Time Delay Estimation via Co-Prime Aliased Sparse FFT

Radix-R WHT-FFT with Identical Stage-to-Stage Interconnection Pattern

Parameterized L1-Minimization Algorithm for Off-the-Gird Spectral Compressive Sensing

A Combinatorial Aliasing-Based Sparse Fourier Transform

A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture

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