Feihui Li

TL;DR: A novel data migration algorithm for parallel applications that models the problem of optimal data placement in the L2 cache space as a two-dimensional post office placement problem, presents a practical architectural implementation of this model, and gives a detailed evaluation of the proposed implementation.

TL;DR: In the proposed approach, the compiler determines the instruction schedule by balancing the permissible performance degradation and the energy constraint with the required degree of duplication, which allows the designer to perform trade-off analysis between performance, reliability, and energy consumption.

TL;DR: A proactive resource partitioning scheme for parallel applications simultaneously exercising the same MPSoC system is explored and shows that it generates much better results than conventional operating system based resource management.

TL;DR: This paper proposes techniques based on load balancing across the integer functional units of VLIW architectures for balanced thermal behavior and peak temperature minimization, and reveals that the peak temperature can be reduced through compiler scheduling.