The Warp machine is a systolic array computer of linearly connected cells, each of which is a programmable processor capable of performing 10 million floating-point operations per second (10 MFLOPS). A typical Warp array includes ten cells, thus having a peak computation rate of 100 MFLOPS. The Warp array can be extended to include more cells to accommodate applications capable of using the increased computational bandwidth. Warp is integrated as an attached processor into a Unix host system. Programs for Warp are written in a high-level language supported by an optimizing compiler. The first ten-cell prototype was completed in February 1986; delivery of production machines started in April 1987. Extensive experimentation with both the prototype and production machines has demonstrated that the Warp architecture is effective in the application domain of robot navigation as well as in other fields such as signal processing, scientific computation, and computer vision research. For these applications, Warp is typically several hundred times faster than a VAX 11/780 class computer. This paper describes the architecture, implementation, and performance of the Warp machine. Each major architectural decision is discussed and evaluated with system, software, and application considerations. The programming model and tools developed for the machine are also described. The paper concludes with performance data for a large number of applications.

/pdf/the-warp-computer-architecture-implementation-and-3b1xpoutwz.pdf

The Warp Computer: Architecture, Implementation, and Performance

We report progress in visual road following by autonomous robot vehicles. We present results and work in progress in the areas of system architecture, image rectification and camera calibration, oriented edge tracking, color classification and road-region segmentation, extracting geometric structure, and the use of a map. In test runs of an outdoor robot vehicle, the Terregator, under control of the Warp computer, we have demonstrated continuous motion vision-guided road-following at speeds up to 1.08 km/hour with image processing and steering servo loop times of 3 sec.

/pdf/progress-in-robot-road-following-5bl6lgh3ea.pdf

Progress in robot road-following

This paper describes the scan line array processor (SLAP), a new architecture designed for high-performance yet low-cost image computation. A SLAP is a SIMD linear array of processors, and hence is easy to build and scales well with VLSI technology; yet appropriate special features and programming techniques make it efficient for a surprisingly wide variety of low and medium level computer vision tasks. We describe the basic SLAP concept and some of its variants, discuss a particular planned implementation, and indicate its performance on computer vision and other applications.

Warp architecture and implementation

Warp is a programmable systolic array processor. One of its objectives is to support computer vision research. This paper shows how the Warp architecture can be used to fulfill the computational needs of low-level vision. We study the characteristics of low-level vision algorithms and show how they lead to requirements for computer architecture. These requirements are met by Warp. We then describe how the Warp system can be used. Warp programs can be classified in two ways: chained versus severed, and heterogeneous versus homogeneous. Chained and severed characterize the degree of interprocessor dependency, while heterogeneous and homogeneous characterize the degree of similarity between programs on individual processors. Taken in combination, these classes give four user models. Sophisticated programming tools are needed to support these user models.

Warp as a machine for low-level vision

A high-performance systolic machine, called Warp, is operational at Carnegie Mellon. The machine has a programmable systolic array of linearly connected cells, each capable of performing 10 million floating-point operations per second. Many image processing operations have been programmed on the machine. This programming experience has yielded new insights in the mapping of image processing operations onto a parallel computer. This paper identifies three major mapping methods that are particularly suited to a Warp-like parallel machine using a linear array of processing elements. These mapping methods correspond to partitioning of input dataset, partitioning of output dataset, and partitioning of computation along the time domain (pipelining). Parallel implementations of several important image processing operations are presented to illustrate the mapping methods. These operations include the Fast Fourier transform (FFT), connected component labelling, Hough transform image warping and relaxation.

/pdf/mapping-image-processing-operations-onto-a-linear-systolic-393oghjspj.pdf

Mapping image processing operations onto a linear systolic machine

A set of two VLSI circuits well-suited for digital signal processing is described which provides the complete 32 bit floating-point multiplier and adder functions. The data format conforms with the new IEEE P754 standard. Operations include multiplication, add, subtract, conversion to and from 24 bit integer numbers and absolute value. Multiply and add times are both 600 nsec in a flow through manner. This is reduced to 200 nsec when operated in a three stage pipeline manner using internal registers. Both chips are fabricated in high-speed NMOS with 3 micron minimum feature size, which results in low power consumption of 1.5 watts typically. They are packaged in 64-pin dual-in-line package and 68-pin leadless-chip-carrier. The applications of this chip set in FFT, digital filtering and array processing are described in this paper.

A high-speech 32 bit IEEE floating-point chip set for digital signal processing

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A high-speech 32 bit IEEE floating-point chip set for digital signal processing