Basic element for the interconnection network of a fast packet switching node, where a synchronization is made at bit input stream level, the cell beginning is identified and a stream conversion from the serial form to a word parallel form is performed. Cells are thus transformed in a completely parallel form and in the same form they are cyclically discharged in the subsequent cell time in a memory (BC), where cells are written and read in a shared way on the basis of instructions given by a control unit (CC), thus performing the switching function. The control unit is essentially based on the use of a content-addressed associative memory, where a fraction of the routing header and a code indicating the time sequence on which the cells arrive are stored. Memory outgoing cells are reconverted from a completely parallel form to a form having the length of one word and therefore in a completely serial form at a bitrate equal to the input one.

Basic element for the connection network of a fast packet switching node

The switching circuit comprises an interface to the interior which comprises two-way gates which are connected to internal interfaces of other switching circuits of said network, each of said gates comprising a l-input and n-output receive circuit and an n-input and l-output transmit circuit, one input of the transmit circuit being connected to the output of a receive circuit different for each of the n inputs, and the input of each receive circuit of a gate being connected to the output of the transmit circuit of a gate of another switching circuit of said network.

Switching circuit for digital packet switching network

A method and system are disclosed for efficiently reading and processing multiple data blocks stored in a removable data storage medium within a data storage system, wherein each data block includes a header portion containing selected parameters necessary to identify and process an associated data block, and a data portion. Each data block is accessed within the removable data storage medium utilizing track logic circuitry and then coupled to a data block buffer for temporary storage. A header processing logic circuit is interposed between the track logic circuitry and the data block buffer and is utilized to initiate processing of only the header portion of each data block prior to storage of the data block within the data block buffer. After completion of processing of the header portion of a data block and completion of storage of that data block within the data block buffer, the data block is efficiently processed utilizing selected parameters contained within the header portion. In this manner, data blocks may be efficiently transferred, processed or coupled to an error recovery procedure from the data block buffer without the delay associated with processing each header portion of a data block after storage of that data block within the data block buffer.

Method and system for preprocessing data block headers during access of data in a data storage system

In a multichannel seismic system, channel-sequential seismic data samples gathered during a first recording cycle are demultiplexed to sample-sequential format in a core memory. The core memory is divided into pages each of which is addressable in two dimensions by rows and columns as a rectangular matrix. The channel-sequential data samples are serially loaded into the respective pages in channel-sequential order by columns. At the end of the first recording cycle, the data are extracted from the respective pages by rows in sample-sequential order. As the data samples from the first recording cycle are being extracted by rows, data samples from a second recording cycle are loaded serially by rows into the respective pages that were vacated by the extracted data samples of the first recording cycle. Data samples from the second recording cycle are then extracted by columns in sample-sequential order and a third set of data samples is loaded serially in vacated elements of the columns, thereafter to be extracted by rows. The process is repeated for the data samples from additional recording cycles.

Method and apparatus for demultiplexing multiplexed seismic data

A programmable serializer comprising a multi-bit input port, a multi-bit output port, at least one multiplexer and at least one programmable address counter corresponding to the multiplexer for generating a sequence of multiplexer data input addresses that are inputted into the multiplexer address input. The multiplexer has an output connected to the multi-bit output port, an address input and a plurality of data input channels having addresses. Each data input channel is connected to a corresponding bit of the multi-bit input port. At least one data input channel is coupled to the multiplexer output when the corresponding address of the data input channel is applied to the address input. The programmable address counter receives and stores an initial address value, an address increment value and a count value and generates a sequence of addresses based on these values. The initial address value represents the multiplexer data channel that is to be initially coupled to the multiplexer output. The address increment value represents the increment that must be added to a current address in order to reach a next address. The count value represents the number of address that must be generated by the counter prior to restarting the sequence at the initial address value.

Programmable serializer using multiplexer and programmable address counter for providing flexiblity in scanning sequences and width of data

Apparatus for transferring messages received at any of four inputs to any of 512 outputs. Messages of 64 bits each may be present on any of four data input lines simultaneously. A 9-bit address identifying an output line is provided with each message on an associated address line. The 64 data bits of each message received during a 64-bit message input period are stored in a memory array. Each of the four data input lines is connected to a delay in the memory array. Each delay has a progressively greater number of delay stages. The last four stages of the four delays are read out in sequence by multiplexers which conduct the data to storage locations. The four most significant bits (MSB) of each address are stored in one memory array and the five least significant bits (LSB) of each address are stored in another memory array. During the next 64-bit period the five LSB''s of the stored addresses are compared with the count of a 5-bit (32 count) counter. When a comparison occurs, the appropriate four MSB''s of the address are read out of the memory array and the 64 data bits are also read out of the memory. The four MSB''s of the address are decoded to select the proper one of sixteen groups of 32 output lines to which the data is to be directed. The 64 bits of data are received in parallel and accepted by the proper output group. Under control of the 5-bit counter, the output group converts the data from parallel to serial form and demultiplexes the serial data to direct it to the proper one of the 32 output lines of the group. The apparatus includes a second set of data and address memories so that a second set of messages can be received and stored while the information in the first set is being read out.

Apparatus for storing several messages received simultaneously

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Apparatus for storing several messages received simultaneously