F. Redaelli
Polytechnic University of Milan
11 Papers
69 Citations
F. Redaelli is an academic researcher from Polytechnic University of Milan. The author has contributed to research in topics: Control reconfiguration & Scheduling (computing). The author has an hindex of 7, co-authored 11 publications.
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Papers
Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs
TL;DR: A new model for the partitioning and scheduling of a specification on partially dynamically reconfigurable hardware is proposed based on a new graph-theoretic approach, which aims to obtain near optimality even if performed independently from the subsequent phase.
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An ILP formulation for the task graph scheduling problem tailored to bi-dimensional reconfigurable architectures
TL;DR: An exact ILP formulation for the task scheduling problem on a 2D dynamically and partially reconfigurable architecture and a reconfiguration-aware heuristic scheduler, which exploits configuration prefetching, module reuse, and antifragmentation techniques are proposed.
An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures
F. Redaelli,Marco D. Santambrogio,Seda Ogrenci Memik +2 more
- 03 Dec 2008
TL;DR: A reconfiguration-aware heuristic scheduler, which exploits configuration prefetching, module reuse, and anti-fragmentation techniques is proposed, which can lead to an overall improvement close to 30% compared to other approaches in literature.
A Reconfiguration-Aware Floorplacer for FPGAs
A. Montone,F. Redaelli,Marco D. Santambrogio,Seda Ogrenci Memik +3 more
- 03 Dec 2008
TL;DR: The goal of this paper is to introduce a partitioning and floorplanning algorithm tailored for reconfigurable architectures deployable on FPGAs that specifically considers the feasibility of the associated communication infrastructure for a given floorplan.
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Floorplacement for partial reconfigurable FPGA-based systems
A. Montone,Marco D. Santambrogio,F. Redaelli,Donatella Sciuto +3 more
- 01 Jan 2011
TL;DR: This work aims at identifying groups of Reconfigurable Functional Units that are likely to be configured in the same chip area, identifying these areas based on resource requirements, device capabilities, and wirelength.