The paper reviews our recent progress and current challenges in implementing advanced gate stacks composed of high-κ dielectric materials and metal gates in mainstream Si CMOS technology. In particular, we address stacks of doped polySi gate electrodes on ultrathin layers of high-κ dielectrics, dual-workfunction metal-gate technology, and fully silicided gates. Materials and device characterization, processing, and integration issues are discussed.

Advanced high-κ dielectric stacks with polySi and metal gates: recent progress and current challenges

Investigations of titanium nitride as metal gate material, elaborated by metal organic atomic layer deposition using TDMAT and NH3

In this letter, we studied the effects of post-deposition anneal (PDA) time and Si interface control layer (ICL) on the electrical characteristics of the MOS capacitor with high-/spl kappa/ (HfO/sub 2/) material on GaAs. Thin equivalent oxide thickness (EOT<3 nm) with excellent capacitance-voltage (C-V) characteristics has been obtained. The thickness of the Si ICL and PDA time were correlated with C-V characteristics. It was found that high temperature Si ICL deposition and longer PDA time at 600/spl deg/C improved the C-V shape, leakage current, and especially frequency dispersion (<5%).

Metal gate-HfO/sub 2/ MOS structures on GaAs substrate with and without Si interlayer

High-κ/metal gate technology is on the verge of replacing conventional oxynitride dielectrics in state-of-the-art transistors for both high-performance and low-power applications. In this review we discuss some of the key materials issues that complicated the introduction of high-κ dielectrics, including reduced electron mobility, oxygen-based thermal instabilities, and the absence of thermally stable dual-metal electrodes. We show that through a combination of materials innovations and engineering ingenuity these issues were successfully overcome, thereby paving the way for high-κ/metal gate implementation.

High-κ/Metal Gate Science and Technology

For the first time, we demonstrate experimentally that by using HfLaO high-kappa gate dielectric, the flat-band voltage (Vfb) and the threshold voltage (Vth) of metal-electrode-gated MOS devices can be tuned effectively in a wide range (wider than that from the Si-conduction band edge to the Si-valence band edge) after a 1000-degC annealing required by a conventional CMOS source/drain activation process. As prototype examples shown in this letter, TaN gate with effective work function Phim,eff~3.9-4.2 eV and Pt gate with Phim,eff~5.5 eV are reported. A specific model based on the interfacial dipole between the metal gate and the HfLaO is proposed to interpret the results. This provides an additionally practical guideline for choosing the appropriate gate stacks and dielectric to meet the requirements of future CMOS devices

Wide $V_{\rm fb}$ and $V_{\rm th}$ Tunability for Metal-Gated MOS Devices With HfLaO Gate Dielectrics

Dual workfunction metal gated MOSFETs with CVD TaSiN, W and Re have been fabricated on HfO/sub 2/. T/sub inv/ as low as 1.46 nm with appropriate Vts and sub-threshold slopes 90 mV/decade or better have been achieved. For the first time we report low damage CVD processes for achieving dual workfunction metal gates in contrast to most reports in literature. Excellent hole mobility has been obtained for aggressive stacks. It is further observed that electron mobility optimization is critically dependent on specific electrode and interface layer combinations along with post deposition processing even for nominally identical HfO/sub 2/ layers.

Dual work function metal gate CMOS using CVD metal electrodes

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Dual work function metal gate CMOS using CVD metal electrodes