Over the last decade, gallium nitride (GaN) has emerged as an excellent material for the fabrication of power devices. Among the semiconductors for which power devices are already available in the market, GaN has the widest energy gap, the largest critical field, and the highest saturation velocity, thus representing an excellent material for the fabrication of high-speed/high-voltage components. The presence of spontaneous and piezoelectric polarization allows us to create a two-dimensional electron gas, with high mobility and large channel density, in the absence of any doping, thanks to the use of AlGaN/GaN heterostructures. This contributes to minimize resistive losses; at the same time, for GaN transistors, switching losses are very low, thanks to the small parasitic capacitances and switching charges. Device scaling and monolithic integration enable a high-frequency operation, with consequent advantages in terms of miniaturization. For high power/high-voltage operation, vertical device architectures are being proposed and investigated, and three-dimensional structures—fin-shaped, trench-structured, nanowire-based—are demonstrating great potential. Contrary to Si, GaN is a relatively young material: trapping and degradation processes must be understood and described in detail, with the aim of optimizing device stability and reliability. This Tutorial describes the physics, technology, and reliability of GaN-based power devices: in the first part of the article, starting from a discussion of the main properties of the material, the characteristics of lateral and vertical GaN transistors are discussed in detail to provide guidance in this complex and interesting field. The second part of the paper focuses on trapping and reliability aspects: the physical origin of traps in GaN and the main degradation mechanisms are discussed in detail. The wide set of referenced papers and the insight into the most relevant aspects gives the reader a comprehensive overview on the present and next-generation GaN electronics.

https://hal.archives-ouvertes.fr/hal-03421528/document

GaN-based power devices: Physics, reliability, and perspectives

This paper reports on the impact of soft- and hard-switching conditions on the dynamic ON-resistance of AlGaN/GaN high-electron mobility transistors. For this study, we used a special double pulse setup, which controls the overlapping of the drain and gate waveforms (thus inducing soft and hard switching), while measuring the corresponding impact on the ON-resistance, drain current, and electroluminescence (EL). The results demonstrate that the analyzed devices do not suffer from dynamic ${R}_{ {\mathrm{\scriptscriptstyle ON}}}$ increase when they are submitted to soft switching up to ${V}_{{\text {DS}}}= 600$ V. On the contrary, hard-switching conditions lead to a measurable increase in the dynamic ON-resistance (dynamic- ${R}_{ \mathrm{\scriptscriptstyle ON}})$ . The increase in dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ induced by hard switching is ascribed to hot-electrons effects: during each switching event, the electrons in the channel are accelerated by the high electric field and subsequently trapped in the AlGaN/GaN heterostructure or at the surface. This hypothesis is supported by the following results: 1) the increase in ${R}_{ \mathrm{\scriptscriptstyle ON}}$ is correlated with the EL signal measured under hard-switching conditions and 2) the impact of hard switching on dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ becomes weaker at high-temperature levels, as the average energy of hot electrons decreases due to the increase scattering with the lattice.

Evidence of Hot-Electron Effects During Hard Switching of AlGaN/GaN HEMTs

Gallium nitride high-electron-mobility transistors (GaN HEMTs) exhibit dynamic on -resistance (d ${R_{\text{on}}}$ ), where the on -resistance immediately after turn- on is higher than the dc value at the same junction temperature. A proliferation of recent literature reports d ${R_{\text{on}}}$ , with some publishing an eight times increase in conduction losses and others finding that the problem is nonexistent. This variation can be largely attributed to the standardized double-pulse-test (DPT) method, which does not specify the blocking time and will ignore any effects that accumulate over multiple switching cycles. With no consistent measurements, designers are left without an accurate conduction loss estimate in converters with GaN HEMTs. We discuss the underlying causes of charge trapping to find the key influences over d ${R_{\text{on}}}$ , and show that the DPT technique gives invalid results. Our measurements validate that each operating parameter must be independently controlled and that only steady-state d ${R_{\text{on}}}$ measurements will predict in situ performance. For the commercial GaN HEMT tested in this letter, the worst-case d ${R_{\text{on}}}$ is nearly two times higher than the dc resistance at the same temperature, confirming that accurate d ${R_{\text{on}}}$ characterization remains critical to predicting converter characteristics. Finally, we provide a reporting framework for GaN HEMT manufacturers and methods to estimate conduction losses in converters with GaN HEMTs.

Dynamic on -Resistance in GaN-on-Si HEMTs: Origins, Dependencies, and Future Characterization Frameworks

We present a GaN monolithic inverter IC on Si substrate and successful motor-drive by it for the first time. Taking advantages of the bi-directional operation free from the forward voltage off-set [1], the inverter can be operated just by the integrated six GaN-based normally-off gate injection transistors (GITs) without any external fast recovery diodes (FRDs) to flow the fly-wheel current. The IC enables the efficiency as high as 93% at low power operation where so far that of conventional Si-based inverters has remained lower value owing to the forward voltage off-set. The key processing technology is the newly introduced planar isolation using Fe ion implantation which fully isolates the GaN-based lateral devices each other.

GaN Monolithic Inverter IC Using Normally-off Gate Injection Transistors

Reliability tests on 600V-rated GaN-based normally-off hybrid-drain-embedded Gate Injection Transistor (HD-GIT) are performed High-temperature reverse-bias test on HD-GIT reveals that the lifetime is dependent on the leakage current before the reliability test Acceleration factors for the temperature and reverse bias voltage are extracted Based on the obtained results, devices are designed so that their lifetimes under Vbs=480V (80% de-rated) at 80°C are longer than 1000 years, which are long enough for most conventional power converter applications Dynamic high-temperature operation life test is also performed, under which their DC characteristics are within their normal range up to 3600h In addition, HD-GITs are within their normal range under the similar reliability tests as applied for Si-based power transistors The physical mechanisms for the reliability of HD-GIT are discussed We conclude that the OFF-state reliability is explained by the so-called percolation degradation model, and that the hole injection from the p-type GaN embedded in the drain plays an important role to suppress the degradation under hard-switching operation test

Reliability of hybrid-drain-embedded gate injection transistor

This paper extends our 650V rated GaN device technology to current ratings in excess of 100A. For the first time, devices with single digit Ron values are reported. A record low value of 6mΩ is measured at 100A. The device technology is shown to be fully current collapse free, over the complete voltage and temperature window. Intrinsic reliability test data up to Vds=900V, and T=200°C is provided. In addition, by using a thicker GaN buffer, 20A rated GaN power devices up to 1.2kV are presented, with leakage current ∼100nA. This is a first step to allow AlGaN/GaN power devices to compete with Si IGBTs and SiC MOSFETs.

AlGaN/GaN power device technology for high current (100+ A) and high voltage (1.2 kV)

This paper reports on the technology and design aspects of an industrial DHEMT process for 650V rated GaN-on-Si power devices, using an in-situ MOCVD grown SiN as surface passivation and gate dielectric, with low interface state density and excellent TDDB. Optimization of the GaN epi stack results in very low off-state leakage (<10nA/mm). Due to the reduction of buffer trapping, low dynamic Ron (<10%) is obtained, both at room temperature and at high temperature.

Technology and design of GaN power devices

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AlGaN/GaN power device technology for high current (100+ A) and high voltage (1.2 kV)

Technology and design of GaN power devices