Copper interconnections and reliability

Evaluation of amorphous (Mo, Ta, W)SiN diffusion barriers for 〈Si〉|Cu metallizations

Over the past decade, the primary focus for improving the performance of nano-electronic metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) delays via utilizing insulating dielectrics with ever lower values of dielectric permittivity. The integration and implementation of such low dielectric constant (i.e. low-k) materials has been fraught with numerous challenges. For intermetal and interlayer (ILD) low-k dielectrics, these challenges have been largely associated to integration with metal interconnect fabrication processes and well documented and reviewed in the literature. Although equally important, less attention has been given to other low-k dielectrics utilized in metal interconnect structures that are commonly referred to as low-k dielectric barriers (DB), etch stops (ES), and/or Cu capping layers (CCL). These materials present numerous challenges as well for integration into metal interconnect fabrication processes. However, they also have more stringent integrated functionality requirements relative to low-k ILD materials that serve only a basic purpose of electrically isolating adjacent metal lines. In this article, we review the integration challenges and associated integrated functionality requirements for low-k DB/ES/CCL materials with a focus on the current status and future direction needed for these materials to facilitate both Moore’s law (i.e. More Moore) and More than Moore scaling. © The Author(s) 2014. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution Non-Commercial No Derivatives 4.0 License (CC BY-NC-ND, http://creativecommons.org/licenses/by-nc-nd/4.0/), which permits non-commercial reuse, distribution, and reproduction in any medium, provided the original work is not changed in any way and is properly cited. For permission for commercial reuse, please email: oa@electrochem.org. [DOI: 10.1149/2.0051501jss] All rights reserved.

https://iopscience.iop.org/article/10.1149/2.0051501jss/pdf

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Ta thin films were grown on Si(001) and polycrystalline Si substrates by plasma-enhanced atomic-layer deposition (PE-ALD) using TaCl5 and atomic hydrogen as precursors. The grown films have resistivity of 150–180 μm cm with a small Cl concentration between 0.5 and 2 at. %. The diffusion barrier properties were investigated using bilayer structures consisting of 200 nm Cu deposited by sputtering on ALD Ta films with various thicknesses. Three in situ analysis techniques consisting of x-ray diffraction, elastic light scattering, and resistance analysis were used to determine the diffusion barrier failure temperature of Ta films. The barriers were annealed at a temperature ramp rate of 3 °C/s from 100 to 1000 °C in forming gas. For this method using x-ray diffraction, the barrier failure temperatures were determined by monitoring the disappearance of the Cu(111) x-ray diffraction peak and appearance of Cu silicide diffraction peaks. At the diffusion barrier failure temperature, elastic light scattering indic...

Diffusion barrier properties of transition metal thin films grown by plasma-enhanced atomic-layer deposition

JSS FOCUS ISSUE ON ADVANCED INTERCONNECTS :M ATERIALS ,P ROCESSING, AND RELIABILITY Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

We demonstrate that depositing Ta diffusion barriers under ultra‐high vacuum conditions without in situ oxygen dosing allows for variations both in microstructure and in the concentration of chemical impurities that severely degrade barrier performance. The effects of deposition pressure, in situ oxygen dosing at interfaces, hydrogen and oxygen contamination, and microstructure on diffusion barrier performance to Cu diffusion for electron‐beam deposited Ta are presented. 20 nm of Ta diffusion barrier followed by a 150 nm Cu conductor were deposited under ultra‐high vacuum (UHV, deposition pressure of 1×10−9 to 5 ×10−8 Torr) and high vacuum (HV, deposition pressure of 1×10−7 to 5×10−6 Torr) conditions onto 〈100〉 Si. In situ resistance furnace measurements, Auger compositional depth profiling, secondary ion mass spectrometry, and forward recoil detection along with scanning and transmission electron microscopy were used to determine the electrical, chemical, and structural changes that occurred in thin‐film Ta diffusion barriers upon annealing. Undosed HV deposited Ta barriers failed from 560 to 630 °C, while undosed UHV barriers failed from 310 to 630 °C. For UHV Ta barriers, in situ oxygen dosing during deposition at the Cu/Ta interface increased the failure temperatures by 30–250 °C and decreased the range of failure temperatures to 570–630 °C. Undosed UHV Ta barriers have no systematic relationship between failure temperature and deposition pressure, although correlations between breakdown temperature, oxygen and hydrogen concentrations, and microstructural variations were measured.

Comparison of high vacuum and ultra‐high‐vacuum tantalum diffusion barrier performance against copper penetration

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Comparison of high vacuum and ultra‐high‐vacuum tantalum diffusion barrier performance against copper penetration