In asymmetric memory systems, the pull-up and pull-down data from the channel can have different amounts of inter-symbol interference (ISI), so they cannot be fully corrected by an equalizer which uses a single tap weight. We introduce a receiver-side single-ended 1-tap asymmetric decision-feedback equalizer (DFE) with a weight selection multiplexer, which allows the application of a different weight to each direction of data value transition. Implemented in a 55-nm CMOS technology, our DFE compensated for asymmetric ISI in a 10.4-Gb/s signal from a channel with an insertion loss of −8.3 dB, leading to a 50% wider horizontal margin at a bit-error-rate of 10−12 than symmetric correction. The energy efficiency is 0.16 pJ/bit.

A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces

This brief presents a 9Gb/s transmitter for intra-panel interfaces, with dual-loop calibration and a 2D binary-segmented driver. The dual-loop calibration during the training period compensates the transmitter output for the variations in operating conditions such as supply voltage and reference current. The 2D binary-segmented driver provides wide range and high resolution output characteristics, and independent adjustments for VOD, VCM and FFE strength while maintaining signal integrity. The transmitter reduces power consumption by optimizing the output for the channel. A prototype chip, fabricated in a 55nm CMOS process, occupies 0.057mm2. It provides FFE strength from 0dB to 26.4dB, common-mode voltage from 260mV to 690mV, and differential output voltage from 100mVppd to 1200mVppd, which varies by less than 4% across supply voltage and reference current variations. It also consumes 36mW at a data-rate of 9Gb/s with a 1.2V supply.

A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces

According to an embodiment, in a display device, pixels have memories respectively. A signal supply circuit includes a mode control circuit, and switches into a first mode or a second mode to supply digital data pieces to sub-pixels. In the first mode, the circuit receives from the outside first video data pieces corresponding to n sub-pixels, and supplies digital data pieces for the n sub-pixels to corresponding memories. In the second mode, the signal supply circuit receives from the outside second video data pieces corresponding to m sub-pixels fewer than n sub-pixels, and supplies digital data pieces for the n sub-pixels to corresponding memories based on the second video data pieces.

Signal supply circuit and display device

The present invention relates to a technology for providing a selection unit configured to perform selection of a bit memory that holds a signal of a first bit of a digital signal from among a plurality of bit memories commonly in a memory unit in each of a plurality of AD conversion units.

Image pickup apparatus, image pickup system, driving method for the image pickup apparatus, and inspection method for the image pickup apparatus

In flat panel display modules with a large-size and high-resolution for TV applications, signaling channels are relatively short on flexible printed circuit (FPC) cable or chip-on-film (COF) package when compared to those of the source PCBs. However, the short distance channels can significantly affect overall signal integrity (SI) performance. Thus, this letter focuses mainly on analysis and design of signal interconnection on FPC cable and COF package in terms of impedance matching and crosstalk. By optimizing the FPC cable design to mitigate crosstalk as well as insertion loss, the opening area of eye diagram was found to be improved more than twice over the previous one. In addition, through adjusting process of on-die capacitance of electro-static discharge (ESD) protection circuitry in the input stage of a high-speed circuit block, the created parasitic inductance of COF package trace was observed to be compensated. This optimization process can improve greatly system performance by widening the input eye opening. Finally, we propose channel design considerations and design guidelines to ensure better SI performance in flexible channels on high-speed intra-panel interface for large-size liquid crystal display (LCD) TV applications. 

SI Considerations in Flexible Channels on High-Speed Intra-Panel Interface for Large-Size Flat Panel Display Applications

42-3: Invited Paper: A 4Gbps/lane Column Driver for 8K UHD 120Hz Display Larger than 85-inches

A method of operating a receiver includes a controller of the receiver determining whether a full initialization or a partial initialization of the receiver is needed; the controller adjusting alternating current (AC) characteristics and direct current (DC) characteristics of the receiver in a full initialization mode, and the controller adjusting the DC characteristics of the receiver in a partial initialization mode when the controller determines the partial initialization is needed.

Operating method of receiver, source driver and display driving circuit including the same

A low-power receiver with a one-tap data and edge decision-feedback equalizer (DFE) and a clock recovery circuit is presented. The receiver employs analog adders for the tap-weight summation in both the data and the edge path to simultaneously optimize both the voltage and timing margins. A switched-capacitor input stage allows the receiver to be fully compatible with near-GND input levels without extra level conversion circuits. Furthermore, the critical path of the DFE is simplified to relax the timing margin. Fabricated in the 65-nm CMOS technology, a prototype DFE receiver shows that the data-path DFE extends the voltage and timing margins from 40 $\hbox{mV}_{\rm pp}$ and 0.3 unit interval (UI), respectively, to 70 $\hbox{mV}_{\rm pp}$ and 0.6 UI, respectively. Likewise, the edge-path equalizer reduces the uncertain sampling region (the edge region), which results in 17% reduction of the recovered clock jitter. The DFE core, including adders and samplers, consumes 1.1 mW from a 1.2-V supply while operating at 6.4 Gb/s.

A 6.4-Gb/s Voltage-Mode Near-Ground Receiver With a One-Tap Data and Edge DFE

A clock and data recovery circuit in accordance with an embodiment of the inventive concept includes a phase locked loop configured to receive a data stream into which an additional bit is inserted at every reference period to generate parallelized data and a clock signal, and a first detector circuit configured to determine whether the parallelized data is locked based on a bit-conversion of the data stream according to an insertion of the additional bit The bit-conversion is executed with respect to the additional bits according to a predetermined protocol, or is executed with respect to at least one bit from among data of the data stream between a current one of the additional bits and a next one of the additional bits

Clock and data recovery circuit detecting unlock of output of phase locked loop

An image sensor is provided. The image sensor includes a converter configured to convert a photoelectric converted analog signal in a unit pixel into a digital signal including a plurality of bits, a data transfer unit configured to selectively output the converted digital signal output from the converter in units of bits in response to a control signal, and including a plurality of switching circuits which are serially connected; and a memory configured to store data output from the data transfer unit.

Device and method of transferring sensed data in image sensor

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