Techniques for measuring and/or compensating for process variations in a semiconductor manufacturing processes. Machine learning algorithms are used on extensive sets of input data, including upstream data, to organize and pre-process the input data, and to correlate the input data to specific features of interest. The correlations can then be used to make process adjustments. The techniques may be applied to any feature or step of the semiconductor manufacturing process, such as overlay, critical dimension, and yield prediction.

Process control techniques for semiconductor manufacturing processes

Real silicon reveals a lot about how new silicon processes work, so test chips are particularly helpful for the semiconductor manufacturers to evaluate a new technology. Traditionally, semiconductor manufacturers relied only on SRAM test chips for ramping up, qualifying and monitoring new semiconductor fabrication processes. Unfortunately, the transistor and circuit geometries used in an SRAM test chip represent only a small fraction of the transistor and circuit geometries found in a real product [BHA98]. In recent years, logic test chip that narrows the gap between the SRAM chips and the real products are used extensively [BHA98] [HES07] [KAR08]. The logic test vehicle is more representative of real product, but may not be as easily testable and diagnosable as the SRAMs. The logic test chips must capture information related to device and interconnect variability, including systematic and random variations, as well as manufacturing features used in lithography, thermal, stress, proximity effects, and they must use all potentially to-be-used library cells. The logic test chips will help manufacture to incorporate silicon-accurate models and enhanced the manufacturing process. In the past, logic test chips are a small function design that contains as more manufacturing features as possible. As for the test chips, the functionality of a chip does not matter. It is required that the test chip must be designed to cover all manufacturing features. It would be feasible if we can design a test chip with many scan cells such that each scan cell contains some manufacturing features to be used, and all scan cells cover all manufacturing features. Testing such a test chip becomes testing all scan cells and their interconnections. In case a failure occurs, diagnosis down to a scan cell can be easily achieved if we use some special scan architectures. In this paper we present the concept of a two-dimensional scan architecture that makes testing and diagnose down to defective scan cells more easily.

On designing two-dimensional scan architecture for test chips

For advanced technologies, the current industry is seeing very complicated silicon defect types and defect distribution. It is very common for the yield of a new design with new technology to start at a very low level and it's critical to ramp up yield as quickly as possible to meet the market window. We propose to use special scan chain test patterns to take advantage special scan chain architecture proposed before. These patterns can achieve perfect diagnostic resolution and hence help to ramp up yield quickly.

Reversible Scan Based Diagnostic Patterns

This paper will look at both technical and business advantages of parallel vs. serial inline parametric testing, secondary effects of changing test strategies, quantifying return on investment of newer test strategies, and next steps in pushing the envelope of test. Topics such as cost, schedule, macro design and quality will be explored to understand tradeoffs and synergies of test strategies. Examples and metrics of parallel compared to serial testing will be examined.

Accelerating 14nm device learning and yield ramp using parallel test structures as part of a new inline parametric test strategy

This paper discusses application of direct charge measurement (DCM) on characterizing on-chip interconnect capacitance. Measurement equipment and techniques are leveraged from Flat Panel Display testing. On-chip active device is not an essential necessity for DCM test structure and it is easy to implement parallel measurements. Femto-Farad measurement sensitivity is achieved without having on-chip active device. Measurement results of silicon and glass substrates, including parallel measurements, are presented.

Benefit of Direct Charge Measurement (DCM) on Interconnect Capacitance Measurement

Continuing scaling trends in semiconductor technology, as well as the test requirements of new technologies being incorporated with mainstream silicon integrated circuits, has increased the complexity of parametric and defect structure testing. New testers are required which can drastically improve the throughput of parametric test, as well as efficiently test new array based process diagnostic structures. Addressing these needs requires merging the traditionally separate functions of digital and parametric test equipment. We describe the development of a new hybrid test system, which combines the features of parametric and digital testers, and in addition introduces a high degree parallelism in its parametric test functions. The test system was developed for high throughput inline test (“parallel test”) of defect structures, semiconductor parametric macros, and advanced array based process monitors down to pA current levels, as well as traditional all digital yield macros, such as SRAMs.

New tools and methodology for advanced parametric and defect structure test

A comprehensive 45 nm short-flow test chip was designed and is currently used to improve defect-limited yield. In a novel development to reduce test time, the DC test structures are tested in parallel mode on a functional test platform, resulting in a 5x reduction in test time over conventional parametric testing. The large critical area enables accurate measurement of defect densities down to the ppb-level, while the reduced cycle time of this short-flow test chip makes it an excellent routine defect monitor as well as a test vehicle for evaluating process changes.

Short-flow test chip utilizing fast testing for defect density monitoring in 45nm

We describe the development and use of various test structures for 32nm yield enhancement. These DC defect test structures are tested in parallel mode on a functional tester using special V/I and Pico-Amp measurement cards. This new test method provides measurement accuracy as high as ± 10 pA along with up to 9x reduction in test time over conventional parametric testing. The large critical area enables reliable estimation of defect densities by failure mechanism.

Test Structures Utilizing High-Precision Fast Testing For 32nm Yield Enhancement

The continuing rise in the number and complexity of test structures required to characterize every new technology generation demands at least a commensurate increase in test throughput. At IBM, various 32nm yield test structures are being tested on a functional test platform using customized Source Measurement Units (SMU) that allow parallel current measurement on up to 100 pins. This novel method improves test throughput as much as 9X over traditional parametric testing while offering current measurement resolution down to 100 fA. The test structures described herein help accelerate yield learning by enabling characterization of yield-loss mechanisms and rapid evaluation of yield improvement actions.

32nm yield learning using efficient parallel-test structures

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New tools and methodology for advanced parametric and defect structure test

Short-flow test chip utilizing fast testing for defect density monitoring in 45nm

Test Structures Utilizing High-Precision Fast Testing For 32nm Yield Enhancement

32nm yield learning using efficient parallel-test structures