Cryptosystem designers frequently assume that secrets will be manipulated in closed, reliable computing environments. Unfortunately, actual computers and microchips leak information about the operations they process. This paper examines specific methods for analyzing power consumption measurements to find secret keys from tamper resistant devices. We also discuss approaches for building cryptosystems that can operate securely in existing hardware that leaks information.

/pdf/differential-power-analysis-4t7fjmuc7b.pdf

Differential Power Analysis

List of Figures. List of Tables. Preface. Foreword. 1. Basic Concepts. 2. Evolutionary Algorithm MOP Approaches. 3. MOEA Test Suites. 4. MOEA Testing and Analysis. 5. MOEA Theory and Issues. 3. MOEA Theoretical Issues. 6. Applications. 7. MOEA Parallelization. 8. Multi-Criteria Decision Making. 9. Special Topics. 10. Epilog. Appendix A: MOEA Classification and Technique Analysis. Appendix B: MOPs in the Literature. Appendix C: Ptrue & PFtrue for Selected Numeric MOPs. Appendix D: Ptrue & PFtrue for Side-Constrained MOPs. Appendix E: MOEA Software Availability. Appendix F: MOEA-Related Information. Index. References.

/pdf/evolutionary-algorithms-for-solving-multi-objective-problems-2txxk4mqci.pdf

Evolutionary algorithms for solving multi-objective problems

In this paper, we provide a systematic comparison of various evolutionary approaches to multiobjective optimization using six carefully chosen test functions. Each test function involves a particular feature that is known to cause difficulty in the evolutionary optimization process, mainly in converging to the Pareto-optimal front (e.g., multimodality and deception). By investigating these different problem features separately, it is possible to predict the kind of problems to which a certain technique is or is not well suited. However, in contrast to what was suspected beforehand, the experimental results indicate a hierarchy of the algorithms under consideration. Furthermore, the emerging effects are evidence that the suggested test functions provide sufficient complexity to compare multiobjective optimizers. Finally, elitism is shown to be an important factor for improving evolutionary multiobjective search.

/pdf/comparison-of-multiobjective-evolutionary-algorithms-2a3t2yk6ku.pdf

Comparison of Multiobjective Evolutionary Algorithms: Empirical Results

An important issue in multiobjective optimization is the quantitative comparison of the performance of different algorithms. In the case of multiobjective evolutionary algorithms, the outcome is usually an approximation of the Pareto-optimal set, which is denoted as an approximation set, and therefore the question arises of how to evaluate the quality of approximation sets. Most popular are methods that assign each approximation set a vector of real numbers that reflect different aspects of the quality. Sometimes, pairs of approximation sets are also considered. In this study, we provide a rigorous analysis of the limitations underlying this type of quality assessment. To this end, a mathematical framework is developed which allows one to classify and discuss existing techniques.

/pdf/performance-assessment-of-multiobjective-optimizers-an-wf8l3c8h73.pdf

Performance assessment of multiobjective optimizers: an analysis and review

Comparison of multiobjective evolutionary algorithms: empirical results

This paper presents two performance-driven Steiner tree algorithms for global routing which consider the minimization of timing delay during the tree construction as the goal One algorithm is based on nonlinear optimization method, another uses heuristic approach to guide the construction of Steiner tree A new timing model is established which includes both total length and critical path between source and sink in delay formulation, and an upper bound for timing delay is deducted and used to guide both algorithms Experiment results are given to demonstrate the effectiveness of the two algorithms

Performance-Driven Steiner Tree Algorithms for Global Routing

We present a new routing region definition and ordering (RRDO) scheme for building block layout. Given an arbitrary placement of rectangular blocks (including the case with cycles in the channel precedence constraints), without modifying the placement, our scheme defines and orders channels so that when a new channel is being routed, its width can be expanded or contracted without destroying the previously routed channels. The cycles in the channel precedence constraints are broken by introducing a new kind of channel--the L-shaped channels. Unlike switchboxes, L-shaped channels can be expanded or contracted to permit the completion of routing without rerouting other existing channels. An efficient greedy RRDO algorithm has been implemented, which tries to generate as few L-shaped channels as possible since L-shaped channels are harder to route than straight channels. Our algorithm represents routing regions by a floor plan graph, for which we provide a precise definition and a construction algorithm. The experimental results of the RRDO algorithm are promising.

Routing Region Definition and Ordering Scheme for Building-Block Layout

The problem of single-row routing represents the backbone of the problem of general routing of multilayer printed circuit boards. In this paper, the necessary and sufficient condition for optimum single-row routing is obtained. By optimum routing we mean minimumm street congestion. A novel formulation is introduced. Examples are given to illustrate how optimum routings are derived. A graph theory interpretation of the condition is also given.

On optimum single-row routing

We present a fast and effective placement algorithm which takes advantage of inherent scarcity in the connectivity specification. It solves repeatedly sparse linear equations by the SOR (Successive Over-Relaxation) method in a top-down hierarchy. The algorithm has been implemented; for a triple-metal-layer 100K sea-of-gates design with 26,000 instances, it takes 50 minutes on a VAX 8650 and yields excellent results.

Proud: a fast sea-of-gates placement algorithm

A new power and ground network design problem for cell-based VLSIs is discussed. In contrast to the conventional method, the network topology is optimized, or wiring resource consumption subject to electromigration and voltage drop constraints is minimized. The proposed method has been implemented. Using several examples, the validity of the problem formulation and the solution method was confirmed. Experimental results showed that brute power bus enhancement was meaningless and smart power and ground topologies significantly reduced the consumption of wiring resources. >

Power and ground network topology optimization for cell based VLSIs

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